Programming Note

All combinations of register addresses specified by Rl

andRa are valid. When the register addresses are

equal, only one word is transmitted. When the address

specified byRa is less than the address specified by R

1

,

the register addresses wrap around from 15 toO. Add

AR RR

lA

7 8 11 12 15

A

RX

5A

7 8 11 12 15 16 1920 31

The second operand is added to the first operand,

and the sum is placed in the first operand location.

Addition is performed by adding all 32 bits of both

operands. If the carries out of the sign-bit position and

the high-order numeric bit position agree, the sum is

satisfactory; if they disagree, an overflow occurs. The

sign bit is not changed after the overflow. A positive

overflow yields a negative final sum, and a negative

overflow results in a positive sum. The overflow causes

a program interruption when the fixed-point overflow

mask bit is one.

Resulting Condition Code:

oSum is zero

1Sum is less than zero

2Sum is greater than zero

3Overflow Program Interruptions:

Addressing (A only)

Specification (A only)

Fixed-point overflow

Programming Note

In two's-complement notation, a zero result is always

positive.

AddHalfword AH RX

4A

7 8 11 12 15 16 1920 31

The halfword second operand is added to the first

operand and the sum is placed in the first operand

location.

The halfword second operand is expanded to a full-

word before the addition by propagating the sign-bit

value through the 16 high-order bit positions.

Addition is performed by adding all 32 bits of both

operands. If the carries out of the sign-bit position

and the high-order numeric bit position agree, the

sum is satisfactory; if they disagree, an overflow oc

curs. The sign bit is not changed after the overflow.

A positive overflow yields a negative final sum, and a

negative overflow results in a positive sum. The over

flow causes a program interruption when the fixed

point overflow mask bit is one.

Resulting Condition Code:

oSum is zero

1Sum is less than zero

2Sum is greater than zero

3 OverflowProgram Interruptions:

Addressing

Specification

Fixed-point overflow

AddLogical ALR RR

1 E

78 11 12 15

AL RX

5E

78 1112 1516 1920 31

The second operand is added to the first operand, and

the sum is placed in the first operand location. The oc

currence of a carry out of the sign position is recorded

in the condition code.

Logical addition is performed by adding all 32 bits

of both operands without further change to the result

ing sign bit. The instruction differs from ADD in the

meaning of the condition code and in the absence of

the interruption for overflow.

If a carry out of the sign position occurs, the leftmost

bit of the condition code (psw bit 34) is made one. In

the absence of a carry, bit 34 is made zero. When the

sum is zero, the rightmost bit of the condition code

(psw bit 35) is made zero. A nonzero sum is indicated

by a one in bit 35.

Resulting Condition Code:

oSum is zero (no carry)

1Sum is not zero (no carry)

2Sum is zero (carry)

3Sum is not zero (carry)

Fixed-Point Arithmetic 27

All combinations of register addresses specified by Rl

and

equal, only one word is transmitted. When the address

specified by

1

,

the register addresses wrap around from 15 to

AR RR

lA

7 8 11 12 15

A

RX

5A

7 8 11 12 15 16 1920 31

The second operand is added to the first operand,

and the sum is placed in the first operand location.

Addition is performed by adding all 32 bits of both

operands. If the carries out of the sign-bit position and

the high-order numeric bit position agree, the sum is

satisfactory; if they disagree, an overflow occurs. The

sign bit is not changed after the overflow. A positive

overflow yields a negative final sum, and a negative

overflow results in a positive sum. The overflow causes

a program interruption when the fixed-point overflow

mask bit is one.

Resulting Condition Code:

o

1

2

3

Addressing (A only)

Specification (A only)

Fixed-point overflow

Programming Note

In two's-complement notation, a zero result is always

positive.

Add

4A

7 8 11 12 15 16 1920 31

The halfword second operand is added to the first

operand and the sum is placed in the first operand

location.

The halfword second operand is expanded to a full-

word before the addition by propagating the sign-bit

value through the 16 high-order bit positions.

Addition is performed by adding all 32 bits of both

operands. If the carries out of the sign-bit position

and the high-order numeric bit position agree, the

sum is satisfactory; if they disagree, an overflow oc

curs. The sign bit is not changed after the overflow.

A positive overflow yields a negative final sum, and a

negative overflow results in a positive sum. The over

flow causes a program interruption when the fixed

point overflow mask bit is one.

Resulting Condition Code:

o

1

2

3 Overflow

Addressing

Specification

Fixed-point overflow

Add

1 E

78 11 12 15

AL RX

5E

78 1112 1516 1920 31

The second operand is added to the first operand, and

the sum is placed in the first operand location. The oc

currence of a carry out of the sign position is recorded

in the condition code.

Logical addition is performed by adding all 32 bits

of both operands without further change to the result

ing sign bit. The instruction differs from ADD in the

meaning of the condition code and in the absence of

the interruption for overflow.

If a carry out of the sign position occurs, the leftmost

bit of the condition code (psw bit 34) is made one. In

the absence of a carry, bit 34 is made zero. When the

sum is zero, the rightmost bit of the condition code

(psw bit 35) is made zero. A nonzero sum is indicated

by a one in bit 35.

Resulting Condition Code:

o

1

2

3

Fixed-Point Arithmetic 27