If the first operand field is too short to contain all
bytes of the second operand, the remaining informa­
tion is ignored. Overlapping fields may occur and are
processed by storing a result byte as soon as the neces­
sary operand bytes are fetched.
Condition Code: The code remains unchanged. Program Interruptions: Protection Addressing
Programming Note
The instruction set for decimal arithmetic includes no
shift instructions since the equivalent of a shift can be
obtained by programming. Programs for right or left
shift and for an even or odd shift amount may be writ­
ten with MOVE WITn OFFSET and the logical move in­
Decimal Arithmetic Exceptions
Exceptional instructions, data, or results cause a pro­
gram interruption. When the interruption occurs, the
current psw is stored as an old PSW, and a new psw is
obtained. The interruption code in the old psw identi­
fies the cause of the interruption. The following ex­
ceptions cause a program interruption in decimal
Operation: The decimal feature is not installed and
or DIVIDE DECIMAL. The instruction is suppressed.
Therefore, the condition code and data in storage and
registers remain unchanged. Protection: The storage key of a result location does
not match the protection key in the psw.
Addressing: An address designates a location out­
side the available storage for the installed system.
In the two preceding exceptions, the operation is
terminated. The result data and the condition code
are unpredictable and should not be used for further
These address exceptions do not apply to the com­
ponents from which an address is generated -the
contents of the Dl and D2 fields and the contents of
the registers specified by Bl and B 2 Specifications: A multiplier or a divisor size ex­
ceeds 15 digits and sign or exceeds the multiplicand
or dividend size. The instruction is suppressed;
therefore, the condition code and data in storage and
registers remain unchanged.
Data: A sign or digit code of an operand in ADD
correct, a multiplicand has insufficient high-order
zeros, or the operand fields in these operations overlap
incorrectly. The operation is terminated. The result
data and the condition code are unpredictable and
should not be used for further computation.
Decimal Overflow: The result of ADD DECIMAL, SUB­ TRACT DECIMAL, or ZERO AND ADD overflows. The pro­
gram interruption occurs only when the decimal-over­ flow mask bit is one. The operation is completed by
placing the truncated low-order result in the result
field and setting the condition code to 3. The sign and
low-order digits contained in the result field are the
same as they would have been for an infinitely long
result field.
Decimal Divide Check: The quotient exceeds the
specified data field, including division by zero. Di­
vision is suppressed. Therefore, the dividend and
divisor remain unchanged in storage.
Decimal Arithmetic 39
Floati nSI-Poi nt Arith metic
The purpose of the floating-point instruction set is to
perform calculations using operands with a wide range
of magnitude and yielding results scaled to preserve
A floating-point number consists of a signcd ex­ ponent and a signed fraction. The quantity expressed
by this number is the product of the fraction and the
number 16 raised to the power of the exponent. The
exponent is expressed in excess 64 binary notation; the
fraction is expressed as a hexadecimal number having
a radix point to the left of the high-order digit.
To avoid unnecessary storing and loading operations
for results and operands, four floating-point registers
are provided. The floating-point instruction set pro­
vides for loading, adding, subtracting, comparing,
multiplying, dividing, and storing, as well as the sign
control of short or long operands. Short operands gen­
erally provide faster processing and require less stor­ age than long operands. On the other hand, long
operands provide greater accuracy of computation.
Operations may be either register to register or storage
to register. All floating-point instructions and registers
are part of the floating-point feature.
To preserve maximum precision, addition, subtrac­
tion, multiplication, and division are performed with
normalized results. Addition and subtraction may also
be performed with unnormalized results. Normalized
and unnormalized operands may be used in any float­ ing-point operation.
The condition code is set as a result of all sign con­ trol, add, subtract, and compare operations.
Data Format
Floating-point data occupy a fixed-length format,
which may be either a fullword short format or a
double-word long format. Both formats may be used
in main storage and in the floating-point registers. The
four floating-point registers are numbered 0, 2, 4,
and 6. Short Floating-Point Number Is I Characteristic I Fraction
o I 78 31 40 Long Floating-Point Number _________ Fr_a_c_ti_o_n ______ ____ o I 7 8 63
The first bit in either format is the sign bit (S). The
subsequent seven bit positions are occupied by the
characteristic. The fraction field may have either six
or 14 hexadecimal digits.
The entire set of floating-point instructions is avail­
able for both short and long operands. When short­
precision is specified, all operands and results are 32-
bit floating-point words, and the rightmost 32 bits of
the floating-point registers do not participate in the
operations and remain unchanged. An exception is the
product in MULTIPLY, which is a 64-bit word and oc­ cupies a full register. When long-precision is specified,
all operands and results are 64-bit floating-point words.
Although final results in short-precision have six
fraction digits, intermediate results in addition, sub­ traction, and division may extend to seven fraction
digits. Thc low-order digit of a seven-digit fraction is
called the guard digit and serves to increase the pre­ cision of the final result. Intermediate results in long­ precision do not exceed 14 fraction digits.
Number Representation
The fraction of a floating-point number is expressed in
hexadecimal digits. The radix point of the fraction is
assumed to be immediately to the left of the high­ order fraction digit. To provide the proper magnitude
for the floating-point number, the fraction is consid­
ered to be multiplied by a power of 16. The character­
istic portion, bits 1-7 of both floating-point formats, in­ dicates this power. The characteristic is treated as an
excess 64 number with a range from -64 through +63,
coresponding to the binary values 0-127.
Both positive and negative quantities have a true
fraction, the difference in sign being indicated by the
sign bit. The number is positive or negative according­
ly as the sign bit is zero or one.
The range covered by the magnitude (M) of a
normalized floating-point number is
in short preciSion 16-
65 L. M L. (1 -16-
) 16
, and
in long precision 16-
65 L. M L. (1 -16-
) 16
or approximately 2.4 . 10-
L. M L. 7.2 . 10
in either precision.
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