A number with zero characteristic, zero fraction, and
plus sign is called a true zero. A true zero may arise
as the result of an arithmetic operation because of the
particular magnitude of the operands. A result is
forced to be true zero when an exponent underflow
occurs or when a result fraction is zero and no pro­
gram interruption due to significance exception is
taken. When the program interruption is taken, the
true zero is not forced, and the characteristic and sign
of the result remain unchanged. Whenever a result has
a zero fraction, the exponent overflow and underflow
exceptions do not cause a program interruption. When
a divisor has a zero fraction, division is omitted, a
floating-point divide exception exists, and a program
interruption occurs. Otherwise, zero fractions and zero
characteristics participate as normal numbers in all
arithmetic operations.
The sign of a sum, difference, product, or quotient
with zero fraction is positive. The sign of a zero
fraction resulting from other operations is established
by the rules of algebra from the operand signs.
Normalization
A quantity can be represented with the greatest pre­
cision by a floating-point number of given fraction
length when that number is normalized. A normalized
floating-point number has a nonzero high-order hex­
adecimal fraction digit. If one or more high-order
fraction digits are zero, the number is said to be un­
normalized. The process of normalization consists of
shifting the fraction left until the high-order hexadeci­
mal digit is nonzero and reducing the characteristic by
the number of hexadecimal digits shifted. A zero frac­
tion can not be normalized, and its associated char­
acteristic therefore remains unchanged when normal­
ization is called for.
Normalization usually takes place when the inter­
mediate arithmetic result is changed to the final result.
This function is called postnol'malization. In perform­
ing multiplication and division, the operands are
normalized prior to the arithmetic process. This func­
tion is called prenol'malization. Floating-point operations may be performed with
or without normalization. Most operations are per­
formed in only one of these two ways. Addition and
subtraction may be specified either way.
When an operation is performed without normaliza­
tion, high-order zeros in the result fraction are not
eliminated. The result mayor may not be normalized,
depending upon the original operands.
In both normalized and unnormalizcd operations,
the initial operands need not be in normalized form.
Also, intermediate fraction results are shifted right
when an overflow occurs, and the intermediate fraction
result is truncated to the final result length after the
shifting, if any.
Programming Note Since normalization applies to hexadecimal digits, the
three high-order bits of a normalized number may be
zero.
Condition Code
The results of floating-point sign-control, add, sub­
tract, and compare operations are used to set the con­
dition code. Multiplication, division, loading, and
storing leave the code unchanged. The condition code
can be used for dec i s ion -m a kin g by sub seq u e n t
branch-on-condition instructions.
The condition code can be set to reflect two types
of results for floating-point arithmetic. For most opera­
tions, the states 0, 1, or 2 indicate the content of the
result register is zero, less than zero, or greater than
zero. A zero result is indicated whenever the result
fraction is zero, including a forced zero. State 3 is used
when the exponent of the result overflows.
For comparison, the states 0, 1, or 2 indicate that the
first operand is equal, low, or high. CONDITION CODE SETTING FOR FLOATING-POINT ARITHMETIC 0 Add Normalized S/L zero
Add Unnormalized slL zero
Compare S/L equal
Load and Test S/L zero
Load Complement S/L zero
Load Negative s/L zero
Load Positive S/L zero
Subtract
Normalized S/L zero
Subtract Un normalized S/L zero
Instruction format
1
< zero
< zero
low
< zero
< zero
< zero
< zero
< zero
2
> zero
> zero
high
> zero
> zero
> zero
> zero
> zero
3
overflow
overflow
overflow
overflow
Floating-point instructions use the following two
formats:
RR Format I Op Code R, R2
o 78 1112 15
RX Format I Op Code R, X
2
B2
o 7 8 11 12 15 16 1 9 20 31
In these formats, Rl designates the address of a float­
ing-point register. The contents of this register will be
Floating-Point Arithmetic 41
called the first operand. The second operand location
is defined differently for two formats.
In the BB format, the R2 field specifies the address
of a floating-point register containing the second op­
erand. The same register may be specified for the first
and second operand.
In the BX format, the contents of the general register
specified by X2 and B2 arc added to the content of the
D2 field to form an address designating the location of
the second operand.
A zero in an X2 or B2 field indicates the absence of
the corresponding address component.
The register address specified by the Rl and R2
fields should be 0, 2, 4 or 6. Otherwise, a specification
exeception is recognized, and a program interruption
is caused.
The storage address of the second operand should
designate word boundaries for short operands and
double-word boundaries for long operands. Otherwise, a specification exception is recognized, and a program
interruption is caused.
Results replace the first operand, except for the stor­
ing operations, where the second operand is replaced.
Except for the storing of the final result, the contents
of all floating-point or general registers and storage
locations participating in the addressing or execution
part of an operation remain unchanged.
The floating-point instructions are the only instruc­
tions using the floating-point registers.
Instructi,ons
The floating-point arithmetic instructions and their
mnemonics, formats, and operation codes follow. All
operations can be specified in short and long precision
and are part of the floating-point feature. The follow­
ing table indicates when normalization occurs, when
the condition code is set, and the exceptions that
cause a program interruption.
NAME
Load (Long)
Load (Long)
Load (Short)
Load (Short)
Load and Test
(Long)
Load and Test
(Short)
Load Complement
(Long)
Load Complement
(Short)
42
MNEMONIC
LDR
LD
LER
LE
LTDR
LTER
LCDR
LCER TYPE RR F
RX F
RR F
RX F
RR F,C
RR F,C
RR F,C
RR F,C EXCEPTIONS S A,S S A,S S S S S CODE 28
68
38
78
22
32
23
33
NAME MNEMONIC TYPE Load Positive (Long) LPDR Load Positive (Short) LPER Load Negative (Long) LNDR
Load Negative (Short) LNER
Add Normalized
(Long)
Add Normalized
(Long)
Add Normalized
( Short) Add N ormaHzed
( Short) Add U nnormalized
(Long)
Add U nnormalized
(Long)
Add Unnormalized
( Short) Add Unnormalized
( Short) Subtract Normalized
(Long) Subtract Normalized
(Long) Subtract Normalized
( Short) Subtract Normalized
( Short) Subtract Unnorm­
alized (Long) Subtract Unnorm­
alized (Long) Subtract Unnorm­
alized (Short) Subtract Unnorm-
alized (Short)
Compare (Long)
Compare (Long)
Compare (Short)
Compare (Short)
Halve (Long)
Halve (Short)
Multiply (Long)
Multiply (Long)
Multiply (Short)
Multiply (Short) Divide (Long)
Divide (Long)
Divide (Short) Divide (Short) Store (Long) Store (Short) NOTES NADR
NAD
NAER
NAE
AWR
AW AUR AU NSDR NSD NSER NSE SWR SW SUR SU CDR
CD
CER
CE
HDR
HER
NMDR
NMD
NMER
NME
NDDR
NDD
NDER
NDE STD STE A Addressing exception
C Condition code is set
RR F,C BR F,C
RR F,C
RR F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RR F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F
RR F
RR F
RX F
RR F
RX F
RR F
RX F
RR F
RX F
RX F
RX F
E Exponent-overflow exception
F Floating-point feature
FK Floating-point divide exception LS Significance exception
N Normalized operation P Protection exception S Specification exception U Exponent-underflow exception EXCEPTIONS CODE S 20 S 30 S 21 S 31 S,U,E,LS 2A A,S, U ,E,LS 6A S,U,E,LS 3A A,S,U,E,LS 7A S, E,LS 2E A,S, E,LS 6E S, E,LS 3E A,S, E,LS 7E S,U,E,LS 2B A,S,U,E,LS 6B S,U,E,LS 3B A,S,U,E,LS 7B S, E,LS 2F A,S, E,LS 6F S, E,LS 3F A,S, E,LS 7F S 29 A,S 69 S 39 A,S 79 S 24 S 34 S,U,E 2C A,S,U,E 6C S,U,E 3C A,S,U,E 7C S,U,E,FK 2D A,S,U,E,FK 6D S,U,E,FK 3D A,S,U,E,FK 7D P,A,S 60 P,A,S 70
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