A number with zero characteristic, zero fraction, and
plus sign is called a true zero. A true zero may arise
as the result of an arithmetic operation because of the
particular magnitude of the operands. A result is
forced to be true zero when an exponent underflow
occurs or when a result fraction is zero and no pro
gram interruption due to significance exception is
taken. When the program interruption is taken, the
true zero is not forced, and the characteristic and sign
of the result remain unchanged. Whenever a result has
a zero fraction, the exponent overflow and underflow
exceptions do not cause a program interruption. When
a divisor has a zero fraction, division is omitted, a
floating-point divide exception exists, and a program
interruption occurs.Otherwise, zero fractions and zero
characteristics participate as normal numbers in all
arithmetic operations.
The sign of a sum, difference, product, or quotient
with zero fraction is positive. The sign of a zero
fraction resulting from other operations is established
by the rules of algebra from the operand signs.
Normalization
A quantity can be represented with the greatest pre
cision by a floating-point number of given fraction
length when that number is normalized. A normalized
floating-point number has a nonzero high-order hex
adecimal fraction digit. If one or more high-order
fraction digits are zero, the number is said to be un
normalized. The process of normalization consists of
shifting the fraction left until the high-order hexadeci
mal digit is nonzero and reducing the characteristic by
the number of hexadecimal digits shifted. A zero frac
tion can not be normalized, and its associated char
acteristic therefore remains unchanged when normal
ization is called for.
Normalization usually takes place when the inter
mediate arithmetic result is changed to the final result.
This function is called postnol'malization. In perform
ing multiplication and division, the operands are
normalized prior to the arithmetic process. This func
tion is calledprenol'malization. Floating-point operations may be performed with
or without normalization. Most operations are per
formed in only one of these two ways. Addition and
subtraction may be specified either way.
When an operation is performed without normaliza
tion, high-order zeros in the result fraction are not
eliminated. The result mayor may not be normalized,
depending upon the original operands.
In both normalized and unnormalizcd operations,
the initial operands need not be in normalized form.
Also, intermediate fraction results are shifted right
when an overflow occurs, and the intermediate fraction
result is truncated to the final result length after the
shifting, if any.
Programming NoteSince normalization applies to hexadecimal digits, the
three high-order bits of a normalized number may be
zero.
Condition Code
The results of floating-point sign-control, add, sub
tract, and compare operations are used to set the con
dition code. Multiplication, division, loading, and
storing leave the code unchanged. The condition code
can be used for dec i s ion -m a kin g by sub seq u e n t
branch-on-condition instructions.
The condition code can be set to reflect two types
of results for floating-point arithmetic. For most opera
tions, the states0, 1, or 2 indicate the content of the
result register is zero, less than zero, or greater than
zero. A zero result is indicated whenever the result
fraction is zero, including a forced zero.State 3 is used
when the exponent of the result overflows.
For comparison, the states0, 1, or 2 indicate that the
first operand is equal, low, or high.CONDITION CODE SETTING FOR FLOATING-POINT ARITHMETIC 0 Add Normalized S/L zero
Add UnnormalizedslL zero
CompareS/L equal
Load and TestS/L zero
Load ComplementS/L zero
Load Negative s/L zero
Load PositiveS/L zero
Subtract
NormalizedS/L zero
SubtractUn normalized S/L zero
Instruction format
1
< zero
< zero
low
< zero
< zero
< zero
< zero
< zero
2
> zero
> zero
high
> zero
> zero
> zero
> zero
> zero
3
overflow
overflow
overflow
overflow
Floating-point instructions use the following two
formats:
RR FormatI Op Code R, R2
o 78 1112 15
RX FormatI Op Code R, X
2
B2
o 7 8 11 12 15 16 1 920 31
In these formats, Rl designates the address of a float
ing-point register. The contents of this register will be
Floating-Point Arithmetic 41
plus sign is called a true zero. A true zero may arise
as the result of an arithmetic operation because of the
particular magnitude of the operands. A result is
forced to be true zero when an exponent underflow
occurs or when a result fraction is zero and no pro
gram interruption due to significance exception is
taken. When the program interruption is taken, the
true zero is not forced, and the characteristic and sign
of the result remain unchanged. Whenever a result has
a zero fraction, the exponent overflow and underflow
exceptions do not cause a program interruption. When
a divisor has a zero fraction, division is omitted, a
floating-point divide exception exists, and a program
interruption occurs.
characteristics participate as normal numbers in all
arithmetic operations.
The sign of a sum, difference, product, or quotient
with zero fraction is positive. The sign of a zero
fraction resulting from other operations is established
by the rules of algebra from the operand signs.
Normalization
A quantity can be represented with the greatest pre
cision by a floating-point number of given fraction
length when that number is normalized. A normalized
floating-point number has a nonzero high-order hex
adecimal fraction digit. If one or more high-order
fraction digits are zero, the number is said to be un
normalized. The process of normalization consists of
shifting the fraction left until the high-order hexadeci
mal digit is nonzero and reducing the characteristic by
the number of hexadecimal digits shifted. A zero frac
tion can not be normalized, and its associated char
acteristic therefore remains unchanged when normal
ization is called for.
Normalization usually takes place when the inter
mediate arithmetic result is changed to the final result.
This function is called postnol'malization. In perform
ing multiplication and division, the operands are
normalized prior to the arithmetic process. This func
tion is called
or without normalization. Most operations are per
formed in only one of these two ways. Addition and
subtraction may be specified either way.
When an operation is performed without normaliza
tion, high-order zeros in the result fraction are not
eliminated. The result mayor may not be normalized,
depending upon the original operands.
In both normalized and unnormalizcd operations,
the initial operands need not be in normalized form.
Also, intermediate fraction results are shifted right
when an overflow occurs, and the intermediate fraction
result is truncated to the final result length after the
shifting, if any.
Programming Note
three high-order bits of a normalized number may be
zero.
Condition Code
The results of floating-point sign-control, add, sub
tract, and compare operations are used to set the con
dition code. Multiplication, division, loading, and
storing leave the code unchanged. The condition code
can be used for dec i s ion -m a kin g by sub seq u e n t
branch-on-condition instructions.
The condition code can be set to reflect two types
of results for floating-point arithmetic. For most opera
tions, the states
result register is zero, less than zero, or greater than
zero. A zero result is indicated whenever the result
fraction is zero, including a forced zero.
when the exponent of the result overflows.
For comparison, the states
first operand is equal, low, or high.
Add Unnormalized
Compare
Load and Test
Load Complement
Load Negative s/L zero
Load Positive
Subtract
Normalized
Subtract
Instruction format
1
< zero
< zero
low
< zero
< zero
< zero
< zero
< zero
2
> zero
> zero
high
> zero
> zero
> zero
> zero
> zero
3
overflow
overflow
overflow
overflow
Floating-point instructions use the following two
formats:
RR Format
o 78 1112 15
RX Format
2
B2
o 7 8 11 12 15 16 1 9
In these formats, Rl designates the address of a float
ing-point register. The contents of this register will be
Floating-Point Arithmetic 41