Load
LER RR(Short Operands) I 38 Rl I R2 0 78 11 12 15
LE RX(Short Operands) I 78 Rl I X
2I B2 0 7 8 11 12 1516 1920 31 LOR RR (Long Operands) I 28 Rl I R2 I 0 7 8 11 12 15 LO RX (Long Operands)
68 RlI X
2I B2
7 8 11 12 15161920 31
The second operand is placed in the first operand
location.
The second operand is not changed. In short-preci
sion the low-order half of the result register remains
unchanged. Exponent overflow, exponent underflow,
or lost significance cannot occur.
Condition Code: The code remains unchanged.Program Interruptions:
Operation (if floating-point feature is not in
stalled)
Addressing (LE, LD only)
Specification
Load and Test
LTER RR
32LTOR RR
22(Short Operands)
RlI R2
7 8 11 12 15
78
(Long Operands)
RlI R2
11 12 15
The second operand is placed in the first operand
location, and its sign and magnitude determine the
condition code.
The second operand is not changed. In short-preci
sion the low-order half of the result register remains
unchanged and is not tested.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3Program Interruptions:
Operation (if floating -point feature is not in
stalled)
Specification
Programming Note
When the same register is specified as first and second
operand location, the operation is equivalent to a test
without data movement.
LoadComplement LCER RR (Short Operands)
33
78 1112 15LCOR RR (Long Operands)
23
78 1112 15
The second operand is placed in the first operand
location with the sign changed to the opposite value.
The sign bit of the second operand is inverted, while
characteristic and fraction are not changed. In short
precision the low-order half of the result register re
mains unchanged and is not tested.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3Program Interruptions:
Operation (if floating-point feature is not in
stalled)
Specification
Load Positive
LPER RR(Short Operands) 30 78 1112 15 LPOR RR (Long Operands) 20 Rl I R2 I 78 1112 15
The second operand is placed in the first operand
location with the sign made plus.
Floating-Point Arithmetic 43
LER RR
LE RX
2
68 Rl
2
7 8 11 12 1516
The second operand is placed in the first operand
location.
The second operand is not changed. In short-preci
sion the low-order half of the result register remains
unchanged. Exponent overflow, exponent underflow,
or lost significance cannot occur.
Condition Code: The code remains unchanged.
Operation (if floating-point feature is not in
stalled)
Addressing (LE, LD only)
Specification
Load and Test
LTER RR
32
22
Rl
7 8 11 12 15
78
(Long Operands)
Rl
11 12 15
The second operand is placed in the first operand
location, and its sign and magnitude determine the
condition code.
The second operand is not changed. In short-preci
sion the low-order half of the result register remains
unchanged and is not tested.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3
Operation (if floating -point feature is not in
stalled)
Specification
Programming Note
When the same register is specified as first and second
operand location, the operation is equivalent to a test
without data movement.
Load
33
78 1112 15
23
78 1112 15
The second operand is placed in the first operand
location with the sign changed to the opposite value.
The sign bit of the second operand is inverted, while
characteristic and fraction are not changed. In short
precision the low-order half of the result register re
mains unchanged and is not tested.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3
Operation (if floating-point feature is not in
stalled)
Specification
Load Positive
LPER RR
The second operand is placed in the first operand
location with the sign made plus.
Floating-Point Arithmetic 43