The operation is identical to EDIT, except for the ad­
ditional function of inserting a byte address in general
register 1. The use of general register 1 is implied.
The byte address is inserted in bits 8-31 of this regis­
ter. The byte address is inserted each time the S trig­
ger is in the zero state and a nonzero digit is inserted
in the result field. The address is not inserted when
significance is forced by the significance-start charac­
ter of the pattern. Bits 0-7 are not changed.
Resulting Condition Code:
o Result field is zero
1 Result field is less than zero
2 Result field is greater than zero
3
Program Interruptions: Operation (if decimal feature is not installed)
Protection
Addressing
Data
Programming Notes
The EDIT AND MARK facilitates the programming of
floating currency-symbol insertion. The character ad­
dress inserted in register 1 is one more than the ad­
dress where a floating currency-sign would be inserted.
The BRANCH ON COUNT, with zero in the R2 field, may
be used to reduce the inserted address by one.
The character address is not stored when signifl­
cance is forced. Therefore, the address of the charac­
ter following the significance-start character should be
placed in register 1 prior to EDIT AND MARK.
When a single instruction is used to edit several
numbers, the address of the first significant digit of
each number is inserted in general register 1. Only the last address will be available after the instruction
is completed. Shift Left Single SI.L RS
89
7 8 11 12 1516 1920 31
The first operand is shifted left the number of bits
specified by the second operand address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
All 32 bits of the general register specified by Rl
participate in the shift. High-order bits are shifted out
without inspection and are lost. Zeros are supplied to
the vacated low-order register positions.
Condition Code: The code remains unchanged.
Program Interruptions: None. Shift Right Single SRL RS
88
7 8 11 12 1516 1920 31
The first operand is shifted right the number of bits
specified by the second operand address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
All 32 bits of the general register specified by Rl
participate in the shift. Low-order bits are shifted out
without inspection and are lost. Zeros are supplied to
the vacated high-order register positions.
Condition Code: The code remains unchanged.
Program Interruptions: None. Shift Left Double
SLDL RS
80
7 8 11 12 1516 1920 31
The double-length first operand is shifted left the
number of bits specified by the second operand ad­
dress.
The Rl field of the instruction specifies an even/odd
pair of registers and must contain an even register
address. An odd value for Rl is a specification excep­
tion and causes a program interruption. The second
operand address is not used to address data; its low­
order six bits indicate the number of bit positions to
be shifted. The remainder of the address is ignored.
All 64 bits of the even/odd register pair specified
by Rl participate in the shift. High-order bits are
shifted out of the even-numbered register without in­
spection and are lost. Zeros are supplied to the va­
cated low-order positions of the odd-numbered regis­
ters.
Condition Code: The code remains unchanged.
Program Interruptions:
Specification
Logical Operations 59
Shift Riglht Double SRDI. RS
8e
7 8 11 12 1516 1920 31
The double-length first operand is shifted right the
number of bits specified by the second operand ad­
dress.
The R L field of the instruction specifies an even/odd
pair of registers and must contain an even register ad­
dress. An odd value for Rl is a specification exception
and causes a program interruption. The second oper­
and address is not used to address data; its low-order
six bits indicate the number of bit positions to be
shifted. The remainder of the address is ignored.
All 64 bits of the even/odd register pair specified
by Rl participate in the shift. Low-order bits are
shifted out of the odd-numbered register without in­
spection and are lost. Zeros are supplied to the va­
cated high-order positions of the registers. Condition Code: The code remains unchanged.
Program Interruptions: S pedfica tion
Programming Note
The logical shifts differ from the arithmetic shifts in
that the high-order bit participates in the shift and is
not propagated, the condition code is not changed,
and no overflow occurs.
Logical Operation Exceptions
Exceptional instructions, data,or results cause a pro­
gram interruption. When the interruption occurs, the
current psw is stored as an old psw and a new psw 60 is obtained. The interruption code in the old psw
identifies the cause of the interruption. The following
exceptions cause a program interruption in logical op­
erations.
Operation: The decimal feature is not installed, and
the instruction is EDIT or EDIT AND MARK. The opera­
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged.
Protection: The storage key of a result location in
storage does not match the protection key in the psw.
The operation is suppressed. Therefore, the condition
code and data in registers and storage remain un­
changed. The only exceptions are the variable-length
storage-to-storage operations, which are terminated.
For terminated operations, the result data and con­
dition code, if affected, are unpredictable and should
not be used for further computation.
Addressing: An address designates a location out­
side the available storage for the installed system. The
operation is terminated. The result data and the con­
dition code, if affected, are unpredictable and should
not be used for further computation.
Specification: A fullword operand in a storage-to­
register operation is not located on a 32-bit boundary
or an odd register address is specified for a pair of
general registers containing a 64-bit operand. The op­
eration is suppressed. Therefore, the condition code
and data in registers and storage remain unchanged.
Data: A digit code of the second operand in EDIT or
EDIT AND MARK is invalid. The operation is terminated.
The result data and the condition code are unpredict­
able and should not be used for further computation. Operand addresses are tested only when used to ad­
dress storage. Addresses used as a shift amount are
not tested. Similarly, the address generated by the use
of LOAD ADDRESS is not tested. The address restrictions
do not apply to the components from which an ad­
dress is generated -the contents of the Dl and D2
fields, and the contents of the registers specified by
X 2 , B1, and B
2
Previous Page Next Page