The operation is identical to EDIT, except for the ad
ditional function of inserting a byte address in general
register 1. The use of general register 1 is implied.
The byte address is insertedin bits 8-31 of this regis
ter. The byte address is inserted each time theS trig
ger is in the zero state and a nonzero digit is inserted
in the result field. The address is not inserted when
significance is forced by the significance-start charac
ter of the pattern. Bits0-7 are not changed.
Resulting Condition Code:
o Result field is zero
1 Result field is less than zero
2 Result field is greater than zero
3
Program Interruptions:Operation (if decimal feature is not installed)
Protection
Addressing
Data
Programming Notes
The EDIT AND MARK facilitates the programming of
floating currency-symbol insertion. The character ad
dress inserted in register 1 is one more than the ad
dress where a floating currency-sign would be inserted.
The BRANCHON COUNT, with zero in the R2 field, may
be used to reduce the inserted address by one.
The character address is not stored when signifl
cance is forced. Therefore, the address of the charac
ter following the significance-start character should be
placed in register 1 prior to EDIT AND MARK.
When a single instruction is used to edit several
numbers, the address of the first significant digit of
each number is inserted in general register 1.Only the last address will be available after the instruction
is completed.Shift Left Single SI.L RS
89
7 8 11 12 1516 1920 31
The first operand is shifted left the number of bits
specified by the second operand address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
All 32 bits of the general register specified by Rl
participate in the shift. High-order bits are shifted out
without inspection and are lost.Zeros are supplied to
the vacated low-order register positions.
Condition Code: The code remains unchanged.
Program Interruptions: None.Shift Right Single SRL RS
88
7 8 11 12 1516 1920 31
The first operand is shifted right the number of bits
specified by the second operand address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
All 32 bits of the general register specified by Rl
participate in the shift. Low-order bits are shifted out
without inspection and are lost.Zeros are supplied to
the vacated high-order register positions.
Condition Code: The code remains unchanged.
Program Interruptions: None.Shift Left Double
SLDL RS
80
7 8 11 12 1516 1920 31
The double-length first operand is shifted left the
number of bits specified by the second operand ad
dress.
The Rl field of the instruction specifies an even/odd
pair of registers and must contain an even register
address. An odd value for Rl is a specification excep
tion and causes a program interruption. The second
operand address is not used to address data; its low
order six bits indicate the number of bit positions to
be shifted. The remainder of the address is ignored.
All 64 bits of the even/odd register pair specified
by Rl participate in the shift. High-order bits are
shifted out of the even-numbered register without in
spection and are lost.Zeros are supplied to the va
cated low-order positions of the odd-numbered regis
ters.
Condition Code: The code remains unchanged.
Program Interruptions:
Specification
LogicalOperations 59
ditional function of inserting a byte address in general
register 1. The use of general register 1 is implied.
The byte address is inserted
ter. The byte address is inserted each time the
ger is in the zero state and a nonzero digit is inserted
in the result field. The address is not inserted when
significance is forced by the significance-start charac
ter of the pattern. Bits
Resulting Condition Code:
o Result field is zero
1 Result field is less than zero
2 Result field is greater than zero
3
Program Interruptions:
Protection
Addressing
Data
Programming Notes
The EDIT AND MARK facilitates the programming of
floating currency-symbol insertion. The character ad
dress inserted in register 1 is one more than the ad
dress where a floating currency-sign would be inserted.
The BRANCH
be used to reduce the inserted address by one.
The character address is not stored when signifl
cance is forced. Therefore, the address of the charac
ter following the significance-start character should be
placed in register 1 prior to EDIT AND MARK.
When a single instruction is used to edit several
numbers, the address of the first significant digit of
each number is inserted in general register 1.
is completed.
89
7 8 11 12 1516 1920 31
The first operand is shifted left the number of bits
specified by the second operand address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
All 32 bits of the general register specified by Rl
participate in the shift. High-order bits are shifted out
without inspection and are lost.
the vacated low-order register positions.
Condition Code: The code remains unchanged.
Program Interruptions: None.
88
7 8 11 12 1516 1920 31
The first operand is shifted right the number of bits
specified by the second operand address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
All 32 bits of the general register specified by Rl
participate in the shift. Low-order bits are shifted out
without inspection and are lost.
the vacated high-order register positions.
Condition Code: The code remains unchanged.
Program Interruptions: None.
SLDL RS
80
7 8 11 12 1516 1920 31
The double-length first operand is shifted left the
number of bits specified by the second operand ad
dress.
The Rl field of the instruction specifies an even/odd
pair of registers and must contain an even register
address. An odd value for Rl is a specification excep
tion and causes a program interruption. The second
operand address is not used to address data; its low
order six bits indicate the number of bit positions to
be shifted. The remainder of the address is ignored.
All 64 bits of the even/odd register pair specified
by Rl participate in the shift. High-order bits are
shifted out of the even-numbered register without in
spection and are lost.
cated low-order positions of the odd-numbered regis
ters.
Condition Code: The code remains unchanged.
Program Interruptions:
Specification
Logical