Instructions are performed by the central process­
ing unit primarily in the sequential order of their
locations. A departure from this normal sequential
operation may occur when branching is performed.
The branching instructions provide a means for mak­
ing a two-way choice, to reference a subroutine, or to ,repeat a segment of coding, such as a loop.
Branching is performed by introducing a branch ad­
dress as a new instruction address.
The branch address may be obtained from one of
the general registers or it may be the address specified
by the instruction. The branch address is independent
of the updated instruction address.
The detailed operation of branching is determined
by the condition code which is part of the program
status word (psw) or by the results in the general reg­
isters which are specified in the loop-closing opera­
tions.
During a branching operation, the rightmost half of
the psw, including the updated instruction address,
may be stored before the instruction address is re­
placed by the branch address. The stored information
may be used to link the new instruction sequence with
the preceding sequence.
The instruction EXECUTE is grouped with the branch­
ing instructions. The branch address of EXECUTE desig­
nates a single instruction to be inserted in the instruc­
tion sequence. The updated instruction address norm­
ally is not changed in this operation, and only the in­
struction located at the branch address is executed.
All branching operations are provided in the stand­
ard instruction set.
Normal Sequential Operation
Normally, operation of the CPU is controlled by in­
structions taken in sequence. An instruction is fetched
from a location specified by the instruction-address field of the psw. The instruction address is increased
by the number of bytes of the instruction to address
the next instruction in sequence. This new instruction­
address value, called the updated instruction address,
replaces the previous contents of the instruction-ad­
dress field in the psw. The current instruction is exe­
cuted, and the same steps are repeated, using the up­
dated instruction address to fetch the next instruction.
Branching
Instructions occupy a halfword or a multiple there­
of. An instruction may have up to three halfwords.
The number of halfwords in an instruction is specified
by the first two instruction bits. A 00 code indicates a
halfword instruction, codes 01 and 10 indicate a two­
halfword instruction, and code 11 indicates a three­
halfword instruction.
Hallword format I OpCode o 78 15
Two-Ha/fword format I Op Code
o
Three-Ha/fword format I Op Code
Bl I o 7 8 1516 1920 3132
Storage wraps around from the maximum address­
able storage location, byte location 16,777,215, to byte
location O. An instruction having its last halfword at
the maximum storage location is followed by the in­
struction at address O. Also, a multiple-halfword in­
struction may straddle the upper storage boundary; no
special indication is given in these cases.
Conceptually, an instruction is fetched from storage
after the preceding operation is completed and before
execution of the current operation, even though physi­
cal storage word size and overlap of instruction execu­
tion with storage access may cause actual instruction
fetching to be different.
A change in the sequential operation may be caused
by branching, status-switching, interruption, or man­
ual intervention. Sequential operation is initiated and
terminated from the system control panel.
Branching 61

Programming Note
It is possible to modify an instruction in storage by
means of the immediately preceding instructions.
Sequenticd Operation Exceptions
Exceptional instruction addresses or operation codes
cause a program interruption. vVhen the interruption
occurs, the current psw is stored as an old PSW, and a
new psw is obtained. The interruption code in the old
psw identifies the cause of the interruption. (In this
manual, part of the description of each class of instruc­
tions is a list of the program interruptions that may
occur for these instructions.) The following program
interruptions may occur in normal instruction sequenc­
ing, independently of the instruction performed.
Operation: The operation code is not assigned.
Addressing: An instruction halfword is located out­
side the available storage for the particular installation.
Specification: The low-order bit of the instruction
address is one.
In each case, the operation is suppressed; therefore,
the condition code and data in storage and registers
remain unchanged. The instruction address stored as
part of the old psw has been updated by the number
of halfwords indicated by the instruction length code
in the old psw.
Programming Notes
An unavailable instruction address may occur when
normal instruction sequencing proceeds from a valid
storage region into an unavailable region or following
a branching or status-switching operation.
The oeld instruction address can occur only follow­
ing branching or status-switching operations.
When the last location in available storage contains
an instruction that again introduces a valid instruction
address, no program interruption is caused, even
though the updated instruction address designates an
unavailable location.
The main-storage or register address specification of
an instruction with unassigned operation code may
cause an addressing or specification interruption when
the requirements for the particular instruction class are
not met. Decisiol1l-Making Branching may be conditional or unconditional. Un­ conditional branches replace the updated instruction
address with the branch address. Conditional branches
may use the branch address or may leave the updated
instruction address unchanged. When branching takes
place, the instruction is called successful; otherwise, it
is called unsuccessful.
62
Whether a conditional branch is successful depends
on the result of operations concurrent with the branch
or preceding the branch. The former case is repre­
sented by BRANCH ON COUNT and the branch-on-index
instructions. The latter case is represented by BRANCH ON CONDITION, which inspects the condition code that reflects the result of a previous arithmetic, logical, or I/O operation.
The condition code provides a means for data-de­
pendent decision-making. The code is inspected to
qualify the execution of the conditional-branch instruc­
tions. The code is set by some operations to reHect the
result of the operation, independently of the previous
setting of the code. The code remains unchanged for
all other operations.
The condition code occupies bit positions 34 and 35
of the psw. When the psw is stored during status­
switching, the condition code is preserved as part of
the psw. Similarly, the condition code is stored as part
of the rightmost half of the psw in a branch-and-link
operation. A new condition code is obtained by a LOAD PSW or SET PROGRAM MASK or by the new psw loaded
as a result of an interruption.
The condition code indicates the outcome of some
of the arithmetic, logical, or I/O operations. It is not
changed for any branching operation, except for EXE­ CUTE. In the case of EXECUTE, the condition code is set
or left unchanged by the subject instruction, as would
have been the case had the subject instruction been in
the normal instruction stream.
The table at the end of this section lists all instruc­
tions capable of altering the condition code and the
meaning of the codes for these instructions.
Instruction Formats
Branching instructions use the following three formats:
RR Format
7 8 11 12 15
RX Format I Op Code I Rl/Mll
X
2
B2 0 7 8 11 12 1516 1920 31
RS Format Op Code Rl R3 B2
7 8 11 12 1516 1920 31