In these formats Rl specifies the address of a gen­
eral register. In BRANCH ON CONDITION a mask field
( M1) identifies the bit values of the condition code.
The branch address is defined differently for the three
formats.
In the RR format, the R2 field specifies the address of
a general register containing the branch address, ex­
cept when R2 is zero, which indicates no branching.
The same register may be specified by Rl and R2.
In the RX format, the contents of the general reg­
isters specified by the X2 and B2 fields are added to
the content of the D2 field to form the branch address.
In the RS format, the content of the general register
specified by the B2 field is added to the content of the
D2 field to form the branch address. The Rg field in
this format specifies the location of the second operand
and implies the location of the third operand. The first operand is specified by the Rl field. The third operand
location is always odd. If the Rg field specifies an even
register, the third operand is obtained from the next
higher addressed register. If the Rg field specifies an
odd register, the third operand location coincides with
the second operand location.
A zero in a B2 or X2 field indicates the absence of
the corresponding address component.
An instruction can specify the same general register
for both address modification and operand location.
The order in which the contents of the general reg­
isters are used for the different parts of an operation
is:
1. Address computation.
2. Arithmetic or link information storage.
3. Replacement of the instruction address by the
branch address obtained under step 1.
Results are placed in the general register specified
by R1. Except for the storing of the final results, the
contents of all general registers and storage locations
participating in the addressing or execution part of an
operation remain unchanged.
Programming Note
In several instructions the branch address may be
specified in two ways: in the RX format, the branch
address is the address specified by X2, B2, and D2, in
the RR format, the branch address is the contents of
the register specified by R2. Note that the relation of
the two formats in branch-address specification is not
the same as in operand-address specification. For op­
erands, the address specified by X2, B2, and D2 is the
operand address, but the register specified by R2 con­
tains the operand itself.
Branching Instructions
The branching instructions and their mnemonics, for­
mats, and operation codes follow. The table also shows
which instructions are not part of the small binary in­
struction set and the exceptions that cause a program
interruption. The subject instruction of EXECUTE fol­
lows its own rules for interruptions. The condition
code is never changed for branching instructions.
NAME
Branch on
Condition
Branch on
Condition
Branch and Link
Branch and Link
Branch on Count Branch on Count Branch on Index
High
Branch on Index
Low or Equal
Execute NOTES MNEMONIC TYPE EXCEPTIONS CODE BCR RR 07 BC RX 47
BALR RR 05 BAL RX 45 BCTR RR 06 BCT RX 46
BXH RS 86
BXLE RS 87
EX RX A,S, EX 44
A Addressing exception
EX Execute exception S Specification exception
Branch On Condition BCR RR I 07 78 1112 15
BC RX
47
7 8 11 12 15 16 19 20 31
The updated instruction address is replaced by the
branch address if the state of the condition code is as
specified by M
1
; otherwise, normal instruction se­
quencing proceeds with the updated instruction ad­
dress.
The Ml field is used as a four-bit mask. The four bits
of the mask correspond, left to right, with the four
condition codes (0, 1, 2, and 3) as follows: CONDITION CODE o
1
2
3 INSTRUCTION BIT
8
9 10 11
The branch is successful whenever the condition
code has a corresponding mask bit of one.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Branching 63

Programming Note
When all four mask bits are ones, the branch is un­
conditional. When all four mask bits are zero or when
the R2 field in the RR format contains zero, the branch
instruction is equivalent to a no-operation.
Branch all1d Link SALR 05 78 1112 15 SAL RX
45
7 8 11 12 15 16 19 20 31
The rightmost 32 bits of the PSW, including the up­
dated instruction address, are stored as link informa­
tion in the general register specified by R I . Subse­ quently, the instruction address is replaced by the
branch address.
The branch address is determined before the link
information is stored. The link information contains
the instruction length code, the condition code, and
the program mask bits, as well as the updated instruc­
tion address. The instruction-length code is 1 or 2,
depending on the format of the BRANCH AND LINK. Condition Code: The code remains unchanged.
Program Interruptions: None.
Programm.'ng Note
The link information is stored without branching when
in the RR format the R2 field contains zero.
When BRANCH AND LINK is the subject instruction of EXECUTE, the instruction-length code is 2.
Branch On Count SCTR RR 06 78 1112 15 SCT RX 46
7 8 11 12 15 16 19 20 31
The content of the general register specified by RI is
algebraically reduced by one. When the result is zero,
normal instruction sequencing proceeds with the up-
64
dated instruction address. When the result is not zero,
the instruction address is replaced by the branch ad­
dress.
The branch address is determined prior to the count­
ing operation. Counting does not change the condition
code. The overflow occurring on transition from the
maximum negative number to the maximum positive
number is ignored. Otherwise, the subtraction pro­
ceeds as in fixed-point arithmetic, and all 32 bits of the
general register participate in the operation.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Programming Notes
Counting is performed without branching when the R2
field in the RR format contains zero.
An initial count of zero is not a special case. It re­
sults in minus one and causes branching to be exe­
cuted.
Branch On Index High
8XH RS 86
7 8 11 12 15 16 19 20 31
The second operand is added to the first operand', and
the sum is compared algebraically with the third op­
erand. Subsequently, the sum is placed in the first
operand location, regardless of whether the branch is
taken. When the sum is high, the instruction address
is replaced by the branch address. When the sum is
low or equal, instruction sequencing proceeds with the
updated instruction address.
The first and the second operands are in the registers
specified hy Rl and R 3 • The third operand register ad­
dress is odd and is either one larger than R3 or equal
to R.'l' The branch address is determined prior to the
addition and comparison. Overflow caused by the addition is ignored and does
not affect the comparison. Otherwise, the addition and
comparison proceed as in fixed-point arithmetic. All
32 bits of the general registers participate in the opera­
tions, and negative quantities are expressed in two's­
complement notation. When the first and third oper­
and locations coincide, the original register contents
are used as third operand.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Programming Note
The name "branch on index high" indicates that one
of the major purposes of this instruction is the incre-