The basic structure of a System/360 consists of main
storage, a central processing unit (cPu), the selector
and multiplexor channels, and the input! output de­
vices attached to the channels through control units.
It is possible for systems to communicate with each
other by means of shared I/O devices, a channel, or
shared storage. Figure 1 shows the basic organization
of a single system.
Main Storage Storage units may be either physically integrated with
the CPU or constructed as stand-alone units. The stor­
age cycle is not directly related to the internal cycling
of the CPU, thus permitting selection of optimum stor­
age speed for a given word size. The physical differ­
ences in the various main-storage units do not affect
the logical structure of the system.
Fetching and storing of data by the CPU are not af­
fected by any concurrent I/O data transfer. If an I/O operation refers to the same storage location as the CPU operation, the accesses are granted in the se­
quence in which they are requested. If the first refer­
ence changes the contents of the location, any sub­
sequent storage fetches obtain the new contents. Con­
current I/O and CPU references to the same storage
location never cause a machine-check indication.
Main
Storage
- Control '-- System Structure
Information Formats
The system transmits information between main stor­
age and the CPU in units of eight bits, or a multiple
of eight bits at a time. An eight-bit unit of information
is called a byte, the basic building block of all formats.
A ninth bit, the parity or check bit, is transmitted
with each byte and carries parity on the bytes. The
parity bit cannot be affected by the program; its only
effect is to cause an interruption when a parity error
is detected. References to the size of data fields and
registers, therefore, exclude the associated parity bits.
All storage capacities are expressed in number of bytes
provided, regardless of the physical word size actually
used.
Bytes may be handled separately or grouped to­
gether in fields. A halfword is a group of two consecu­
tive bytes and is the basic building block of instruc­
tions. A word is a group of four consecutive bytes; a
double word is a field consisting of two words (Figure
2). The location of any field or group of bytes is spe­
cified by the address of its leftmost byte.
The length of fields is either implied by the oper­
ation to be performed or stated explicitly as part of
the instruction. When the length is implied, the in­
formation is said to have a fixed length, which can be
either one, two, four, or eight bytes.
When the length of a field is not implied by the Input/ I 1 - Output c Unit c f---t - Device ....c: U f-----t c-- .... f---i Q) 1 f-----t ""5 f---i ::E f----i Central Processing t- Input/ Unit Control t-- I-- Output f------\ Unit t- Device W c f---t t-- C c f---t ....c: U --I .... .8 --I u Q) --I W Vl --I Figure 1. IBM System/360 Basic Logical Structure
System Structure 7

operation code, but is stated explicitly, the informa­
tion is said to have variable field length. Variable­
length operands are variable in length by increments
of one byte.
Within any program format or any fixed-length op­
erand format, the bits making up the format are con­
secutively numbered from left to right starting with
the number O. Byte Halfword 11 0 0 1 Jo 0 0 1 11 0 1 0 KO 0 1 01 15
Word 11 0 0 011 0 0 111 0 0 0 BO 0 1 011 0 0 1'1> 1 0 011 1 1 0 1 11 16 24 31
Figure 2. Sample Information Formats
Addressing
Byte locations in storage are consecutively numbered
starting with 0; each number is considered the ad­
dress of the corresponding byte. A group of bytes in
storage is addressed by the leftmost byte of the group.
The addressing capability permits a maximum of
16,777,216 bytes, using a 24-bit binary address. This
set of main-storage addresses includes some locations
reserved for special purposes.
Storage addressing wraps around from the maximum
byte address, 16,777,215, to address O. Variable-length
operands may be located partially in the last and par­
tially in the first location of storage, and are processed
without any special indication.
When only a part of the maximum storage capacity
is available in a given installation, the available stor­
age is normally contiguously addressable, starting at
address O. An addressing exception is recognized
when any part of an operand is located beyond the
maximum available capacity of an installation.
In some models main storage may be shared by
more than one CPU. In that case, the address of a byte
location is normally the same for each CPU. Informatic)n Positioning Fixed-length fields, such as halfwords and double
words, must be located in main storage on an integral
boundary for that unit of information. A boundary is
called integral for a unit of information when its stor-
8
age address is a multiple of the length of the unit in
bytes. For example, words (four bytes) must be lo­
cated in storage so that their address is a multiple of
the number 4. A halfword (two bytes) must have an
address that is a multiple of the number 2, and double
words (eight bytes) must have an address that is a
multiple of the number 8.
Storage addresses are expressed in binary form. In
binary, integral boundaries for halfwords, words, and
double words can be specified only by the binary ad­
dresses in which one, two, or three of the low-order
bits, respectively, are zero. (Figure 3). For example,
the integral boundary for a word is a binary address
in which the two low-order positions are zero.
Varia ble fields are not limited to integral bounda­
ries' but may start on any byte location.
Binary 0000 0001 0010 0011 0100 01Ql 0110 0111 1000 1001 1010 Address
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Halfword Halfword Halfword Halfword Halfword , l Word Word Word -( Double-Word Double-Word
Figure 3. Integral Boundaries for Halfwords, Words, and
Doublewords
Central Processing Unit ) l
The central processing unit (Figure 4) contains the
facilities for addressing main storage, for fetching or
storing information, for arithmetic and logical proc­
essing of data, for sequencing instructions in the de­
sired order, and for initiating the communication be­
tween storage and external devices.
The system control section provides the normal CPU control that guides the CPU through the operation
necessary to execute the instructions. While the
physical make-up of the control section in the various
models of the Systems/360 may be different, the
logical function remains the same.
The CPU provides 16 general registers for fixed-point
operands and four floating-point registers for floating­
point operands. Implementation of these registers may
be in active elements, in a local storage unit, or in a
separate area of main storage. In each case, the ad­
dress and functions of these registers are identical. , l