Storage Address
r- -'- -lOll( I I Instructions I Co mputer I I Sys tem I I Co ntrol , ..... Indexed Address I I I I I I L_
__ .-J Fixed Point
Operations MAIN STORAGE Variable Field Length
Operations J Floating Point
16 General Registers I Floating Point Registers
Figure 4. Central Processing Unit General Registers
The CPU can address information in 16 general regis­
ters. The general registers can be used as index regis­
ters, in address arithmetic and indexing, and as ac­
cumulators in fixed-point arithmetic and logical oper­ ations. The registers have a capacity of one word (32
bits). The general registers are identified by numbers 0-15 and are selected by a four-bit field in the in­ struction called the R field (Figure 5).
R Field Reg No. General Registers Floating Point Registers 0000 0 !i±32 Bits. hi:"":.'::::"': 64 Bits :::':":::::::::::::::;1I!l:1 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6
....... ,,' .. ··· .. ·'·:1 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14
1111 15
Figure 5. General and Floating-Point Registers
For some operations, two adjacent registers can be
coupled together, providing a two-word capacity.
In these operations, the addressed register contains
the high-order operand bits and must have an even
address, while the implied register, containing the
low-order operand bits, has the next higher address. Floating-Point Registers
Four floating-point registers are available for floating­ point operations. These registers are two words (64
bits) in length and can contain either a short (one
word) or a long (two word) floating-point operand.
A short operand occupies the high-order bits of a
floating-point register. The low-order portion of the
register is ignored and remains unchanged in short­ precision arithmetic. The floating-point registers are
identified by the numbers 0, 2, 4, and 6 (Figure 5).
The operation code determines which type of register
is to be used in an operation.
Arithmetic and Logical Unit
The arithmetic and logical unit can process binary in­
tegers and floating-point fractions of fixed length, deci­ mal integers of variable length, and logical information
of either fixed or variable length. Processing may be in System Structure 9
parallel or in series; the width of the arithmetic unit,
the multiplicity of the shifting paths, and the degree
of simultaneity in performing the different types of
arithmetic differ from one CPU to another without af­
fecting the logical appearance of the design.
Arithmetic and logical operations performed by the CPU fall into four classes: fixed-point arithmetic, deci­
mal arithmetic, floating-point arithmetic, and logical
operations. These classes differ in the data formats
used, the registers involved, the operations provided,
and the way the field length is stated.
Fixed-Point Arithmetic
The basic arithmetic operand is the 32-bit fixed-point
binary word. Sixteen-bit halfword operands may be
specified in most operations for improved performancc
or storage utilization. See Figure 6. To preserve
precision, some products and all dividends are 64 bits
o 1 15
o 1 31
Figure 6. Fixed-Point Number Formats
Because the 32-bit word size conveniently accom­
modates a 24-bit address, fixed-point arithmetic can
be used both for integer operand arithmetic and for
address arithmetic. This combined usage provides
economy and permits the entire fixed-point instruction
set and several logical operations to be used in ad­
dress computation. Thus, multiplication, shifting, and
logical manipulation of address components are pos­
The absence of recomplementation and the ease of
extension and truncation make two's-complement no­
tation desirable for address components and fixed­ point operands. Since integer and addressing algorisms
often require repeated reference to operands or inter­
mediate results, the use of multiple registers is advan­
tageous in arithmetic sequences and address calcula­
Additions, subtractions, multiplications, divisions,
and comparisons are performed upon one operand in
a register and another operand either in a register or
from storage. Multiple-precision operation is made
convenient by the two's-complement notation and by
recognition of the carry from one word to another. A
word in one register or a double word in a pair of
adjacent registers may be shifted left or right. A pair
of conversion instructions - CONVERT TO BINARY and CONVERT TO DECIMAL -provides transition between
decimal and binary radix (number base) without the
use of tables. Multiple-register loading and storing in­
structions facilitate subroutine switching. Decimal Arithmetic
Decimal arithmetic is designed for processes requiring
few computational steps between the source input
and the documented output. This type of processing
is frequently found in commercial applications, par­
ticularly when use is made of problem-oriented lan­
guages. Because of the limited number of arithmetic
operations performed on each item of data, radix con­
version from decimal to binary and back to decimal
is not justified, and the use of registers for intermedi­
ate results yields no advantage over storage-to-storage
processing. Hence, decimal arithmetic is provided,
and both operands and results are located in storage.
Decimal arithmetic includes addition, subtraction,
multiplication, division, and comparison.
Decimal numbers are treated as signed integers with
a variable-field-length format from one to 16" bytes
long. Negative numbers are carried in true form.
The decimal digits 0-9 are represented in the four­
bit binary-cod ed-decimal form by 0000-1001, respec­
tively. The codes 1010-1111 are not valid as digits and
are reserved for sign codes; 1011 and 1101 represent
a minus; the other four codes are interpreted as plus.
The sign codes generated in decimal arithmetic de­
pend upon the character set preferred (Figure 7).
When the expanded binary coded decimal interchange
code (EBCDIC) is preferred, the codes are 1100 and 1101. When the ASCII set, expanded to eight bits, is
preferred, the codes are 1010 and 1011. The choice
between the two code sets is determined by a mode
Decimal operands are represented by four-bit bin­
ary-coded-decimal digits packed two to a byte. They
appear in fields of variable length and are accompa­
nied by a sign in the rightmost four bits of the low-
Digit Code Sign Code 0 0000 + 1010 1 0001 - 1011 2 0010 + 1100 3 0011 - 1101 4 0100 + 1110 5 0101 + 1111
6 0110 7 0111 8 1000 9 1001 Pigure 7. Bit Codes for Digits and Signs
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