Storage Address
r--'- -lOll( I I Instructions I Co mputer I I Sys tem I I Co ntrol , ..... Indexed Address I I I I I I L_
__.-J Fixed Point
OperationsMAIN STORAGE Variable Field Length
OperationsJ Floating Point
Operations
4
16General Registers I Floating Point Registers
Figure 4. Central ProcessingUnit General Registers
TheCPU can address information in 16 general regis
ters. The general registers can be used as index regis
ters, in address arithmetic and indexing, and as ac
cumulators in fixed-point arithmetic and logicaloper ations. The registers have a capacity of one word (32
bits). The general registers are identified by numbers0-15 and are selected by a four-bit field in the in struction called the R field (Figure 5).
RField Reg No. General Registers Floating Point Registers 0000 0 !i±32 Bits. hi:"":.'::::"': 64 Bits :::':":::::::::::::::;1I!l:1 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6
.......,,' .. ··· .. ·'·:1 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14
1111 15
Figure 5. General and Floating-Point Registers
For some operations, two adjacent registers can be
coupled together, providing a two-word capacity.
In these operations, the addressed register contains
the high-order operand bits and must have an even
address, while the implied register, containing the
low-order operand bits, has the next higher address.Floating-Point Registers
Four floating-point registers are available forfloating point operations. These registers are two words (64
bits) in length and can contain either a short (one
word) or a long (two word) floating-point operand.
A short operand occupies the high-order bits of a
floating-point register. The low-order portion of the
register is ignored and remains unchanged inshort precision arithmetic. The floating-point registers are
identified by the numbers0, 2, 4, and 6 (Figure 5).
The operation code determines which type of register
is to be used in an operation.
Arithmetic and Logical Unit
The arithmetic and logical unit can process binary in
tegers and floating-point fractions of fixed length,deci mal integers of variable length, and logical information
of either fixed or variable length. Processing may be inSystem Structure 9
r-
__
Operations
Operations
Operations
4
16
Figure 4. Central Processing
The
ters. The general registers can be used as index regis
ters, in address arithmetic and indexing, and as ac
cumulators in fixed-point arithmetic and logical
bits). The general registers are identified by numbers
R
.......
1111 15
Figure 5. General and Floating-Point Registers
For some operations, two adjacent registers can be
coupled together, providing a two-word capacity.
In these operations, the addressed register contains
the high-order operand bits and must have an even
address, while the implied register, containing the
low-order operand bits, has the next higher address.
Four floating-point registers are available for
bits) in length and can contain either a short (one
word) or a long (two word) floating-point operand.
A short operand occupies the high-order bits of a
floating-point register. The low-order portion of the
register is ignored and remains unchanged in
identified by the numbers
The operation code determines which type of register
is to be used in an operation.
Arithmetic and Logical Unit
The arithmetic and logical unit can process binary in
tegers and floating-point fractions of fixed length,
of either fixed or variable length. Processing may be in