Instruction Execution
An interruption occurs when the preceding instruction
is finished and the next instruction is not yet started.
The manner in which the preceding instruction is
finishcd may be influenced by the cause of the inter­
ruption. The instruction is said to have been com­
pleted, terminated, or suppressed.
In the case of instruction completion, results are
stored and the condition code is set as for normal in­
struction operation, although the result may be influ­
enced by the exception which has occurred.
In the case of instruction termination, all, part, or
none of the result may be stored. Therefore, the result
data are unpredictable. The setting of the condition
code, if called for, may also be unpredictable. In
general, the results should not be used for further
In the case of instruction suppression, the execution
proceeds as if no operation were specified. Results
are not stored, and the condition code is not changed.
Source Identification
The five classes of interruptions are distinguished by
the storage locations in which the old psw is stored
and from which the new psw is fetched. The detailed
causes are further distinguishcd by the interruption
code of the old psw, except for the machine-check
interruption. The bits of the interruption code are
numbered 16-31, according to their position in the psw.
For 110 interruptions, additional information is pro­
vided by the contents of the channel status word
stored as part of the 110 interruption.
For machine-check interruptions, additional infor­
mation is provided by the diagnostic procedure, which
is part of the interruption.
The following table lists the permanently allocated
main-storage locations. ADDRESS LENGTH PURPOSE a 0000 0000 Double word Initial program loading PSW 8 0000 1000 Double word Initial program loading CCW1
16 00010000 Double word Initial program loading CCW2
24 0001 1000 Double word External old PSW 32 0010 0000 Double word Supervisor call old PSW 40 0010 1000 Double word Program old PSW 48 0011 0000 Double word Machine old PSW 56 00111000 Double word Input/output old PSW 64 0100 0000 Double word Channel status word
72 0100 1000 Word Channc1 address word
76 0100 1100 Word Unused 80 0101 0000 Word Timer
84 0101 0100 Word Unused
88 0101 1000 Double word External new PSW 96 0110 0000 Double word Supervisor call new PSW 104 0110 1000 Double word Program new PSW 112 0111 0000 Double word Machine-check new PSW 120 0111 1000 Double word Input/output new PSVV 128 1000 0000 Diagnostic scan-out areal) I)Thc size of the diagnostic scan-out mea depends on the par-
ticular model and I/O channels.
Location Determination
For some interruptions, it is desirable to locate the in­
struction being interpreted when the interruption oc­
curred. Since the instruction address in the old psw
designates the instruction to be executed next, it is
necessary to know the lcngth of the preceding instruc­
tion. This length is recorded in bit positions 32 and
33 of the psw as the instruction-length code.
The instruction-length code is predictable only for
program and supervisor-call interruptions. For I/O
and external interruptions, the interruption is not
caused by the last-interpreted instruction, and the
code is not predictable for these instructions. For
machine-check interruptions, the setting of the code
may be affected by the malfunction and, therefore, is
For the supervisor-caB interruption, the instruction­
length code is 1, indicating the halfword length of SUPERVISOR CALL. For program interruptions, the codes
1, 2, and 3 indicate the instruction length in halfwords.
The code 0 is reserved for program interruptions
where the length of the instruction is not available be­
cause of certain overlapping conditions in struction
fetching. In code-O cases, the instruction address in
the old psw does not represent the next instruction
address. Instruction-length code 0 can occur for a
program interruption only when the interruption is
caused by a protected or an unavailable data address.
The following table shows the states of the instruction­
1 01 00 One halfword RR
2 10 01 Two halfwords RX
2 10 10 Two halfwords RS or SI 3 11 11 Three halfwords SS Programming Notes
When a program interruption is due to an incorrect
branch address, the location determined from the in­
struction address and instruction-length code is the
branch address and not the location of the branch
When an interruption occurs while the CPU is in the
wait state, the instruction-length code is always unpre­
The instruction EXECUTE represents upon interrup­
tion an instruction-length code which docs not reflect
thc length of the instruction executed, but is 2, the
length of EXECUTES.
Interruptions 77
Input/Output Interruption
The 1/ () interruption provides a means by which the CPU responds to signals from I/O devices.
A request for an I/O interruption may occur at any
time, and more than one request may occur at the
same time. The requests are preserved in the I/O section until accepted by the CPU. Priority is estab­
lished among requests so that only one interruption
request is processed at a time.
An I/O interruption can occur only after execution
of the current instruction is completed and while the CPU is interruptable for the channel presenting the
request. Channels are masked by system mask bits 0-6. Interruptions masked off remain pending.
The I/O interruption causes the old psw to be stored
at location 56 and causes the channel status word as­
sociated with the interruption to be stored at location
64. Subsequently, a new psw is loaded from location 120. The interruption code in the old psw identifies the
channel and device causing the interruption in bits
21-23 and 24-31, respectively. Bits 16-20 of the old psw
are made zero. The instruction-length code is unpre­
Program Interruption
Exceptions resulting from improper specification or
use of instructions and data cause a program interrup­
The current instruction is completed, terminated, or
suppressed. Only one program interruption occurs for
a given instruction and is identified in the old psw.
The occurrence of a program interruption docs not
preclude the simultaneous occurrence of other pro­
gram-interruption causes. Which of several causes is
identified may vary from one occasion to the next and
from one model to another.
A program interruption can occur only when the
corresponding mask bit, if any, is one. When the mask
bit is zero, the interruption is ignored. Program inter­
ruptions do not remain pending. Program mask bits
36-39 permit masking of four of the 15 interruption
The program interruption causes the old psw to be
stored at location 40 and a new psw to be fetched
from location 104. The cause of the interruption is identified by inter­
ruption-code bits 28-31. The remainder of the interrup­
tion code, bits 16-27 of the PSW, are made zero. The
instruction-length code indicates the length of the
preceding instruction in halfwords. For a few cases,
the instruction length is not available. These cases are
indicated by code O. A description of the individual program exceptions
follows. The application of these rules to each class of
instructions is further described in the applicable sec­
tions. Some of the exceptions listed may also occur in
operations executed by I/O channels. In that event, the
exception is indicated in the channel status word
stored with the I/O interruption (as explained under "Input/Output Operations"). Operation Exception
When an operation code is not assigned or the as­
signed operation is not available on the particular
model, an operation exception is recognized. The op­
eration is suppressed.
The instruction-length code is 1, 2, or 3.
Privileged-Operation Exception
When a privileged instruction is encountered in the
problem state, a privileged-operation exception is rec­
ognized. The operation is suppressed.
The instruction-length code is 1 or 2.
Execute Exception
When the subject instruction of EXECUTE is another
EXECUTE, an execute exception is recognized. The
operation is suppressed.
The instruction-length code is 2.
Protection Exception
When the storage key of a result location does not
match the protection key in the PSW, a protection ex­
ception is recognized.
The operation is suppressed, except in the case of STORE MULTIPLY, READ DIRECT, and variable-length op­
erations, which are terminated.
The instruction-length code is 0, 2, or 3.
Addressing Exception
When an address specifies any part of data, an in­
struction, or a control word outside the available
storage for the particular installation, an addressing
exception is recognized.
The operation is terminated for an invalid data
address. Data in storage remain unchanged, except
when designated by valid addresses. The operation is
suppressed for an invalid instruction address.
The instruction-length code normally is 1, 2 or 3;
but may be 0 in the case of a data address.
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