Specification Exception
A specification exception is recognized when:
1. A data, instruction, or control-word address does
not specify an integral boundary for the unit of in­
formation.
2. The Rl field of an instruction specifies an odd
register address for a pair of general registers that
contains a 64-bit operand.
3. A floating-point register address other than 0, 2,
4, or 6 is specified.
4. The multiplier or divisor in decimal arithmetic
exceeds 15 digits and sign.
5. The first operand field is shorter than or equal to
the second operand field in decimal multiplication or
division.
6. The block address specified in SET STORAGE KEY or
INSERT STORAGE KEY has the four low-order bits not
all zero.
7. A psw with nonzero protection key is loaded
and the protection feature is not installed.
The operation is suppressed. The instruction-length
code is 1, 2, or 3.
Data Exception
A data exception is recognized when:
1. The sign or digit codes of operands in decimal
arithmetic or editing operations or in CONVERT TO BINARY are incorrect.
2. Fields in decimal arithmetic overlap incorrectly.
3. The decimal multiplicand has too many high­
order significant digits.
The operation is terminated. The instruction-length
code is 2 or 3.
Fixed-Point-Overflow Exception
When a high-order carry occurs or high-order signifi­
cant bits are lost in fixed-point add, subtract, shift, or
sign-control operations, a fixed-point-overflow excep­
tion is recognized.
The operation is completed by ignoring the infor­
mation placed outside the register. The interruption
may be masked by psw bit 36.
The instruction-length code is 1 or 2.
Fixed-Point-Divide Exception
A fixed-point-divide exception is recognized when a
quotient exceeds the register size in fixed-pOint divi­
sion, including division by zero, or the result of CON­ VERT TO BINARY exceeds 31 bits.
Division is suppressed. Conversion is completed by
ignoring the information placed outside the register.
The instruction-length code is 1 or 2. Decimal-Overflow Exception
When the destination field is too small to contain the
result field in a decimal operation, a decimal-overflow
exception is recognized.
The operation is completed by ignoring the overflow
information. The interruption may be masked by psw
bit 37.
The instruction-length code is 3.
Decimal-Divide Exception
When a quotient exceeds the specified data field
size, a decimal-divide exception is recognized. The
operation is suppressed.
The instruction-length code is 3.
Exponent-Overflow Exception
When the result characteristic exceeds 127 in floating­
point addition, subtraction, multiplication, or division,
an exponent-overflow exception is recognized. The
operation is terminated.
The instruction-length code is 1 or 2. Exponent-U nderflow Exception
When the result characteristic is less than zero in
floating-point addition, subtraction, multiplication, or
division, an exponent-underflow exception is rec­
ognized.
The operation is completed by making the result a
true zero. The interruption may be masked by psw
bit 38.
The instruction-length code is 1 or 2.
Significance Exception
When the result of a floating-point addition or sub­
traction has an all-zero fraction, a significance excep­
tion is recognized.
The operation is completed. The interruption may
be masked by psw bit 39. The manner in which the
operation is completed is determined by the mask bit.
The instruction-length code is 1 or 2.
Floating-Point-Divide Exception
When division by a floating-point number with zero
fraction is attempted, a floating-point divide exception
is recognized. The operation is suppressed.
The instruction-length code is 1 or 2.
Supervisor-Col/Interruption
The supervisor-call interruption occurs as a result of
the execution of SUPEHVISOR CALL.
The supervisor-call interruption causes the old psw
to be stored at location 32 and a new psw to be
fetched from location 96.
Interruptions 79

The contents of bit positions 8-15 of the SUPERVISOR CALL become bits 24-31 in the interruption code of the
old psw. Bits 16-23 of the interruption code are made
zero. The instruction-length code is 1, indicating the
halfword length of SUPERVISOR CALL. Programming Notes
The name "supervisor call" indicates that one of the
major purposes of the interruption is the switching
from problem to supervisor state. This major purpose
does not preclude the use of this interruption for other
types of status-switching.
The jnterruption code may be used to convey a
message from the calling program to the supervisor.
When SUPERVISOR CALL is performed as the subject
instruction of EXECUTE, the instruction-length code is 2.
External Interruption
The external interruption provides a means by which
the CPU responds to signals from the timer, from the
interrupt key, and from external units.
A request for an external interruption may occur at
any time, and requests from diHerent sources may
occur at the same time. Requests are preserved until
honored by the CPU. All pending requests are pre­
sented simultaneously when an external interruption
occurs. Each request is presented only once. When
several requests from one source are made before the
interruption is taken, only one interruption occurs.
An external interruption can occur only when sys­
tem mask bit 7 is one and after execution of the cur­
rent instruction is completed. The interruption causes
the old psw to be stored at location 24 and a new
psw to be fetched from location 88.
The source of the interruption is identified by inter­
ruption-code bits 24-31. The remainder of the interrup­
tion code, psw bits 16-23, is made zero. The instruc­
tion-length code is unpredictable for external inter­
ruptions.
Timer
A timer value changing from positive to negative
causes an external interruption with bit 24 of the in­
terruption code turned on.
Timer 111111111 23 24 25 26 27 28 29 30 31
The timer occupies a 32-bit word at storage location
80. In the standard form, the contents of the timer are
reduced by a one in bit position 21 and in bit position 80 23 every 1/60th of a second or the timer contents are
reduced by one in bit position 21 and in bit position 22
every 1/50th of a second. The choice is determined by
the available line frequency. The gross result in either
case is equivalent to reducing the timer by one in bit
position 23 every 1/300th of a second.
Higher resolution may be obtained in some models
by counting with higher frequency in one of the posi­
tions 24 through 31. In each case, the frequency is ad­
justed to give counting at 300 cycles per second in bit
23, as shown in the table. The full cycle of the timer
is 15.5 hours.
BIT POSITION FREQUENCY RESOLUTION 23 300 cps 3.33 ms
24 600 cps 1.67 ms
25 1.2 kc 833 fLS 26 2.4 kc 417 fLS 27 4.8 kc 208 fLS 28 9.6 kc 104 fLS 29 19.2 kc 52 fLS 30 38.4 kc 26 fLS 31 76.8 kc . 13 fLS The count is treated as a signed integer by following
the rules for fixed-pOint arithmetic. The negative over­
flow, occurring as the timer is counted from a large
negative number to a large positive number, is ig­
nored. The interruption is initiated as the count pro­
ceeds from a positive number, including zero, to a
negative number.
The timer is updated whenever access to storage
permits. An updated timer value is normally available
at the end of each instruction execution; thus, a real­
time count can be maintained. Timer updating may he
omitted when I/O data transmission approaches the
limit of storage capability and when the instruction
time for READ DIRECT is excessive.
After an interruption is initiated, the timer may
have been updated several times before the CPU is
actually interrupted, depending upon instruction exe­
cution time.
The timer remains unchanged when the CPU is in
the stopped state or when the rate switch on the
operator intervention panel is set to INSTRUCTION STEP. The timer value may be changed at any time by
storing a new value in storage location 80 (except
when this location is protected).
The timer is an optional feature on some models.
Programming Note
The timer in association with a program can serve both
as a real-time clock and as an interval timer. Interrupt Key
Pressing the interrupt key on the operator control
section of the system control panel causes an external