interruption with bit 25 of the interruption code
turned on.
The key is active while power is on. External Signal An external signal causes an external interruption,
with the corresponding bit in the interruption code
turned on.
A total of six signal-in lines may be connected to
the CPU for receiving external signals. The pattern
presented in interruption-code bits 26-31 depends
upon the pattern received before the interruption is
The external signals are part of the direct control
Programming Note
The signal-in lines of one CPU may be connected to the
signal-out timing lines of the direct control feature or
the machine check out-line of the multisystem feature
of another CPU. An interconnection of this kind allows
one CPU to interrupt another. Also, the direct-out lines
of one CPU may be connected to the direct-in lincs of
the other, and vice versa.
Machine-Check Interruption
The machine-check interruption provides a means for
recovery from and fault location of machine malfunc­
When the machine-check mask bit is one, occur­
rence of a machine check terminates the current in­
struction, initiates a diagnostic procedure, issues a
signal on the machine check out-line, and subsequent­
ly causes the machine-check interruption.
The old psw is stored at location 48 with an inter­
ruption code of zero. The state of the CPU is scanned
out into the storage area, starting with location 128
and extending through as many words as the given CPU requires. The new psw is fetched from location
112. Proper execution of these steps depends on the
nature of the machine check.
The machine check out-signal is provided as part of
the multisystem feature. The signal is a O.5-micro­
second to l.O-mierosecond timing signal that follows
the I/O interface line-driving and terminating specifi­
cations. The signal is designed so that it has a high
probability of being issued in the presence of machine
When the machine-check mask bit is zero, an at­
tempt is made to complete the current instruction
upon the occurrence of a machine check and to pro­
ceed with the next sequential instruction. No diagnos­
tic procedure, signal, or interruption occurs.
A change in the machine-check mask bit due to the
loading of a new psw results in a change in the treat­
ment of machine checks. Depending on the nature of
a machine check, the earlier treatment may still be in
force for several cycles.
Following emergency power turn-off and turn-on
or system reset, incorrect parity may exist in storage
or registers. Unless new information is loaded, a ma­
chine check may occur erroneously. Once storage and
registers are cleared, a machine check can be caused
only by machine malfunction and never by data or in­
Machine checks occurring in operations executed
by I/O channels either cause a machine-check inter­
ruption or are recorded in the channel status word for
that operation.
Priority of Interruptions
During execution of an instruction, several interrup­
tion-causing events may occur simultaneously. The
instruction may give rise to a program interruption, an
external interruption may occur, a machine check may
occur, and an I/O interruption request may be made.
Instead of the program interruption, a supervisor-call might occur; however, both cannot occur
since these two interruptions are mutually exclusive.
Simu1taneous interruption requests are honored in a
predetermined order.
The machine-check interruption has highest priority.
When it occurs, the current operation is terminated.
Program and supervisor-call interruptions that would
have occurred as a result of the current instruction are
eliminated. Every reasonable attempt is made to limit
the side-effects of a machine check. Normally, I/O and
external interruptions, as well as the progress of the I/O data transfer and the updating of the timer, re­
main unaffected.
When no machine check occurs, the program inter­
ruption or supervisor-call interruption is taken first, the
external interruption is taken next, and the I/O inter­
ruption is taken last. The action consists of storing the
old psw and fetching the new psw belonging to the
interruption first taken. This new psw is subsequently
stored without any instruction execution, and the next
interruption psw is fetched. This storing and fetching
continues until no more interruptions are to be serv­
iced. The external and I/O interruptions are taken only
if the immediately preceding psw indicates that the CPU is interruptable for these causes.
Instruction execution is resumed using the last­
fetched psw. The order of executing interruption sub­
routines is therefore the reverse of the order in which
the psw's arc fetched.
Interruptions 81
The interruption code of a new psw is not loaded
since a new interruption code is always storcd. The
instruction-length code in a new psw is similarly ig­
nored since it is unpredictable for all interruptions
other than program or supcrvisor call. The protcction
key of a new psw is stored unchanged when the pro­
tection feature is installed. When the feature is not
installed, the protection key is made zero upon storing.
Programming Note
When interruption sources are not masked off, thc
order of priority in handling the intcrruption sub­
routines is machine check, I/O, external, and program
or supervisor call. This order can be changed to some
extent by masking. The priority rule applies to inter­
ruption requests made simultaneously. An interruption
request made after some interruptions have already
been taken is honored according to the priority pre­
vailing at the moment of request.
Interruption Exceptions
The only exception that can cause a program inter­
ruption during an interruption is a specification ex­
Specification: The protection feature is not installed,
and a new psw with nonzero protection kcy is loaded.
A program interruption is taken immediately upon
loading thc new PSW, regardless of the type of inter­
ruption introducing thc erroneous protection key and
prior to any other pending interruptions. The protec­
tion key is made zero when the psw is stored.
If the new psw for the program interruption has a
nonzero protection key, another program interruption
occurs. Since this second program interruption intro­
duces the same unacceptable protection key in the
new PSW, the process is repeated with the CPU caught
in a string of program interruptions. This string can be
broken only by initial program loading or system reset.
The instruction address in a new psw is not tested
for availability or resolution as the psw is fetched
during an interruption. However, an unavailable or
odd instruction address is detected as soon as the
instruction address is used to fetch an instruction.
These exceptions are described in the section on
normal sequential operation.
If the new psw for the program interruption has an
unacceptable instruction address, another program
interruption occurs. Since this second program inter­
ruption introduces the same unaccept'able instruction
address, a string of program interruptions is estab­
lished. This string may be broken by an external or I/O interruption. If these interruptions also have an
unacceptable new psw, new supervisor information
must be introduced by initial program loading or by
manual intervention.
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