interruption with bit 25 of the interruption code
turned on.
The key is active while power is on.External Signal An external signal causes an external interruption,
with the corresponding bit in the interruption code
turned on.
A total of six signal-in lines may be connected to
theCPU for receiving external signals. The pattern
presented in interruption-code bits 26-31 depends
upon the pattern received before the interruption is
taken.
The external signals are part of the direct control
feature.
Programming Note
The signal-in lines of oneCPU may be connected to the
signal-out timing lines of the direct control feature or
the machine check out-line of the multisystem feature
of anotherCPU. An interconnection of this kind allows
oneCPU to interrupt another. Also, the direct-out lines
of oneCPU may be connected to the direct-in lincs of
the other, and vice versa.
Machine-Check Interruption
The machine-check interruption provides a means for
recovery from and fault location of machine malfunc
tion.
When the machine-check mask bit is one, occur
rence of a machine check terminates the current in
struction, initiates a diagnostic procedure, issues a
signal on the machine check out-line, and subsequent
ly causes the machine-check interruption.
The old psw is stored at location 48 with an inter
ruption code of zero. The state of theCPU is scanned
out into the storage area, starting with location 128
and extending through as many words as the givenCPU requires. The new psw is fetched from location
112. Proper execution of these steps depends on the
nature of the machine check.
The machine check out-signal is provided as part of
the multisystem feature. The signal is a O.5-micro
second to l.O-mierosecond timing signal that follows
theI/O interface line-driving and terminating specifi
cations. The signal is designed so that it has a high
probability of being issued in the presence of machine
malfunction.
When the machine-check mask bit is zero, an at
tempt is made to complete the current instruction
upon the occurrence of a machine check and to pro
ceed with the next sequential instruction. No diagnos
tic procedure, signal, or interruption occurs.
A change in the machine-check mask bit due to the
loading of a new psw results in a change in the treat
ment of machine checks. Depending on the nature of
a machine check, the earlier treatment may still be in
force for several cycles.
Following emergency power turn-off and turn-on
or system reset, incorrect parity may exist in storage
or registers. Unless new information is loaded, a ma
chine check may occur erroneously.Once storage and
registers are cleared, a machine check can be caused
only by machine malfunction and never by data or in
structions.
Machine checks occurring in operations executed
byI/O channels either cause a machine-check inter
ruption or are recorded in the channel status word for
that operation.
Priority of Interruptions
During execution of an instruction, several interrup
tion-causing events may occur simultaneously. The
instruction may give rise to a program interruption, an
external interruption may occur, a machine check may
occur, and anI/O interruption request may be made.
Instead of the program interruption, a supervisor-call might occur; however, both cannot occur
since these two interruptions are mutually exclusive.
Simu1taneous interruption requests are honored in a
predetermined order.
The machine-check interruption has highest priority.
When it occurs, the current operation is terminated.
Program and supervisor-call interruptions that would
have occurred as a result of the current instruction are
eliminated. Every reasonable attempt is made to limit
the side-effects of a machine check. Normally,I/O and
external interruptions, as well as the progress of theI/O data transfer and the updating of the timer, re
main unaffected.
When no machine checkoccurs, the program inter
ruption or supervisor-call interruption is taken first, the
external interruption is taken next, and theI/O inter
ruption is taken last. The action consists of storing the
old psw and fetching the new psw belonging to the
interruption first taken. This new psw is subsequently
stored without any instruction execution, and the next
interruption psw is fetched. This storing and fetching
continues until no more interruptions are to be serv
iced. The external andI/O interruptions are taken only
if the immediately preceding pswindicates that the CPU is interruptable for these causes.
Instruction execution is resumed using the last
fetched psw. The order of executing interruption sub
routines is therefore the reverse of the order in which
the psw's arc fetched.
Interruptions 81
turned on.
The key is active while power is on.
with the corresponding bit in the interruption code
turned on.
A total of six signal-in lines may be connected to
the
presented in interruption-code bits 26-31 depends
upon the pattern received before the interruption is
taken.
The external signals are part of the direct control
feature.
Programming Note
The signal-in lines of one
signal-out timing lines of the direct control feature or
the machine check out-line of the multisystem feature
of another
one
of one
the other, and vice versa.
Machine-Check Interruption
The machine-check interruption provides a means for
recovery from and fault location of machine malfunc
tion.
When the machine-check mask bit is one, occur
rence of a machine check terminates the current in
struction, initiates a diagnostic procedure, issues a
signal on the machine check out-line, and subsequent
ly causes the machine-check interruption.
The old psw is stored at location 48 with an inter
ruption code of zero. The state of the
out into the storage area, starting with location 128
and extending through as many words as the given
112. Proper execution of these steps depends on the
nature of the machine check.
The machine check out-signal is provided as part of
the multisystem feature. The signal is a O.5-micro
second to l.O-mierosecond timing signal that follows
the
cations. The signal is designed so that it has a high
probability of being issued in the presence of machine
malfunction.
When the machine-check mask bit is zero, an at
tempt is made to complete the current instruction
upon the occurrence of a machine check and to pro
ceed with the next sequential instruction. No diagnos
tic procedure, signal, or interruption occurs.
A change in the machine-check mask bit due to the
loading of a new psw results in a change in the treat
ment of machine checks. Depending on the nature of
a machine check, the earlier treatment may still be in
force for several cycles.
Following emergency power turn-off and turn-on
or system reset, incorrect parity may exist in storage
or registers. Unless new information is loaded, a ma
chine check may occur erroneously.
registers are cleared, a machine check can be caused
only by machine malfunction and never by data or in
structions.
Machine checks occurring in operations executed
by
ruption or are recorded in the channel status word for
that operation.
Priority of Interruptions
During execution of an instruction, several interrup
tion-causing events may occur simultaneously. The
instruction may give rise to a program interruption, an
external interruption may occur, a machine check may
occur, and an
Instead of the program interruption, a supervisor-call
since these two interruptions are mutually exclusive.
Simu1taneous interruption requests are honored in a
predetermined order.
The machine-check interruption has highest priority.
When it occurs, the current operation is terminated.
Program and supervisor-call interruptions that would
have occurred as a result of the current instruction are
eliminated. Every reasonable attempt is made to limit
the side-effects of a machine check. Normally,
external interruptions, as well as the progress of the
main unaffected.
When no machine check
ruption or supervisor-call interruption is taken first, the
external interruption is taken next, and the
ruption is taken last. The action consists of storing the
old psw and fetching the new psw belonging to the
interruption first taken. This new psw is subsequently
stored without any instruction execution, and the next
interruption psw is fetched. This storing and fetching
continues until no more interruptions are to be serv
iced. The external and
if the immediately preceding psw
Instruction execution is resumed using the last
fetched psw. The order of executing interruption sub
routines is therefore the reverse of the order in which
the psw's arc fetched.
Interruptions 81