The operation is suppressed, except in the case of
NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE STORE MULTIPLE, READ DIRECT, and variable-length op-
AND NI SI C P,A, 94 SPR erations, which are terminated.
AND NC SS C P,A D4 TRM
The instruction-length code is 0, 2, or 3. Compare C RX C A,S, 59 TRM Compare NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE Decimal CP SS T,C A, D F9 TRM
Add Decimal AP SS T,C P,A, D, DF FA TRM Compare AND NI SI C P,A 94 SPR Halfword CH RX C A,S, 49 TRM
AND NC SS C P,A D4 TRM Compare Convert to
Logical CL RX C A,S, 55 TRM
Decimal CVD RX P,A,S 4E SPR Compare Divide Decimal DP SS T P,A,S,D, DK FD TRM
Logical CLI SI C A 95 TRM
Edit ED SS T,C P,A, D DE TRM Compare Edit: and Mark EDMK SS T,C P,A, D DF TRM
Logical CLC SS C A D5 TRM Exclusive OR XI SI C P,A 97 SPR Compare (Long) CD RXF,C A,S, 69 TRM
Exclusive OR XC SS C P,A D7 TRM Compare (Short) CE RXF,C A,S, 79 TRM
Move MVI SI P,A 92 SPR Convert to
Move MVC SS P,A D2 TRM
Binary CVB RX A,S,D, IK 4F TRM
Move Numerics MVN SS P,A D1 TRM Convert to
Move with
Decimal CVD RX P,A,S, 4E SPR Offset MVO SS P,A F1 TRM Diagnose SI M, A,S, 83 SPR Move Zones MVZ SS P,A D3 TRM Divide D RX A,S, IK 5D TRM
Multiply Divide Decimal DP SS T P,A,S,D, DK FO TRM
Decimal MP SS T P,A,S,D FC TRM Divide (Long) NDD RXF A,S,U,E,FK 60 TRM OR 01 SI C P,A 96 SPR Divide (Short) NDE RXF A,S,U,E,FK 70 THM OR OC SS C P,A D6 TRM Edit ED SS T,C P,A, D DE TRM Pack PACK SS P,A F2 TRM Edit and Mark EDMK SS T,C P,A, D DF TRM
Read Direct RDD SI Y M,P,A 85 TRM Exclusive OR X RX C A,S, 57 TRM Store ST RX P,A,S 50 SPR Exclusive OR XI SI C P,A, 97 SPR Store Character STC RX P,A 42 SPR Exclusive OR XC SS C P,A, D7 TRM Store Halfword STH RX P,A,S 40 SPR Execute EX RX A,S, EX 44 SPR Store Long STD RXF P,A,S 60 SPR Insert Character IC RX A 43 TRM Store Insert Storage
Multiple STM RXF P,A,S 90 TRM
Key ISK RRZ M, A,S 09 Store Short STE RXF P,A,S 70 SPR Subtract
Load L RX A,S, 58 TRM
Decimal SP SS T,C P,A, D, DF FB TRM
Load Halfword LH RX A,S, 48 TRM
Translate TR SS P,A DC TRM
Load (Long) LD RXF A,S, 68 TRM Unpack UNPK SS P,A F3 TRM
Load Multiple LM RS A,S, 98 TRM Zero and Add ZAP SS T,C P,A, D, DF F8 TRM
Load PSW LPSW SI LM, A,S 82 TRM
Load (Short) LE RXF A,S, 78 TRM PROTECTION INTERRUPTION NOTES Move MVI SI P,A 92 SPR SPR = Operation suppressed Move MVC SS P,A D2 TRM
TRM = Operation terminated Move Numerics MVN SS P,A D1 TRM
Addressing (A)
Move with Offset MVO SS P,A Fl TRM
Move Zones MVZ SS P,A D3 TRM
An address specifies any part of data, instructions, or Multiply M RX A,S 5C TRM
control words outside the available storage for the par-
Multiply
ticular installation.
Decimal MP SS T P,A,S,D FCTRM Multiply
The operation is terminated. Data in storage remain IIalfword MH RX A,S 4C TUM unchanged, except when designated by valid ad-
Multiply (Long) NMD RXF A,S,U,E 6C -;"'RM dresses.
Multiply (Short) NME RXF A,S,U,E 7C TUM The instruction-length code normally is 2 or 3; but OR 0 RX C A,S, 56 TRM OR 01 SI C P,A 96 SPR may be 0, in the case of a data address. OR OC SS C P,A D6 TRM
NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE Pack PACK SS P,A F2 TRM
Add A RX C A,S, IF 5A TRM
Read Direct RDD SI Y M,P,A, 85 TRM
Add Decimal AP SS T,C P,A D, DF FA TRM Set Storage Key SSK RRZ M, A,S 08 Add Halfword AH RX C A,S, IF 4A TRM Set System Mask SSM SI M, A 80 TRM
Add Logical AL RX C A,S, 5E TRM Store ST RX P,A,S 50 SPR Add Normalized Store Character STC RX P,A 42 SPR (Long) NAD RXF,C A,S,U,E,LS 6A TRM Store Halfword STH RX P,A,S 40 SPR Add Normalized Store (Long) STD RXF P,A,S 60 SPR ( Short) NAE RXF,C A,S,U,E,LS 7A TRM Store Multiple STM RS P,A,S 90 TRM
Add Unnorm- Store (Short) STE RXF P,A,S 70 SPR alized (Long) AW RXF,C A,S, E,LS 6E TRM Subtract S RX C A,S, IF 5B TRM
Add Unnorm-Subtract Decimal SP SS T,C P,A, D, DF FB TRM
alized (Short) AU RXF,C A,S, E,LS 7E TRM Subtract
AND N RX C A,S, 54 TRM Halfword SH RX C A,S, IF 4B TRM
Appendix G 149
NAME MNEMONIC TYPE Subtract Logical SL RX C
Subtract Norm-
alized (Long) N SD RX F,C
Subtract Norm-
alized (Short) N SE RX F,C
Subtract Un- normalized
(Long)
Subtract Un­ normalized
( Short)
Test Under Mask
Translate
Translate and
Test SW RX F,C SU RX F,C
TM SI C
TR SS TRT SS C UNPK SS EXCEPTIONS CODE NOTE A,S 5F TRM A,S,U,E,LS 6B TRM A,S,U,E,LS 7B TRM
A,S, E,LS 6F TRM
A,S, E,LS 7F TRM
A 91 TRM P,A DC TRM
A DDTRM P,A F3 TRM Unpack Write Direct
Zero and Add 'VRD SI Y M, A 84 TRM ZAP SS T,C P,A, D, DF F8 TRM
The addressing interruption can occur in normal sequential
operation following branching, LOAD PSW, interruption, or man­
ual operation.
Instruction execution is suppressed.
ADDRESSING INTERRUPTION NOTES SPR Operation suppressed
TRM = Operation terminated Specification (S) 1. A data, instruction, or control-word address does
not specify an integral boundary for the unit of in­
formation.
2. The Rl field of an instruction specifies an odd
register address for a pair of general registers that
contain a 64-bit operand.
3. A floating-point register address other than 0, 2,
4, or 6 is specified.
4. The multiplier or divisor in decimal arithmetic
exceeds 15 digits and sign.
5. The first operand field is shorter than or equal to
the second operand field in decimal multiplication or
division.
6. The block address specified in SET STORAGE KEY
or INSERT STORAGE KEY has the four low-order bits not
all zero.
7. A psw with nonzero protection key is loaded
when the protection feature is not installed.
In all of these cases the operation is suppressed.
The instruction-length code is 1, 2, or 3.
NAME MNEMONIC Add A
Add Halfword AH
Add Logical AL
Add Normalized
(Long) N ADR
Add Normalized
(Long) N AD
Add Normalized
( Short) N AER
Add NormaHzed
(Short) N AE 150 TYPE RX C
RX C
RX C
RRF,C
RXF,C
RRF,C
RXF,C EXCEPTIONS A,S,
A,S, A,S CODE NOTE IF 5A 4
IF 4A 2
5E 4 S,U,E,LS 2A 3 A,S,U,E,LS 6A 3,8 S,U,E,LS 3A 3 A,S,U,E,LS 7A 3,4
NAME
Add Unnorm­ alized (Long)
Add Unnorm­ alizcd (Long)
Add Un norm­
alized (Short)
Add Unnorm­ alized (Short)
AND
Compare
Compare
I Ialfword
Compare
Logical
Compare
(Long)
Compare
(Long)
Compare
( Short) Compare
( Short)
Convert to
Binary
Convert to
Decimal
Diagnose
Divide
Divide
Divide Dccimal
Dividc (Long)
Divide (Long)
Divide (Short)
Divide (Short) Exclusive OB Execute
Halve (Long)
Halve (Short)
Insert Storage Key
Load
Load and Test (Long) I,oad and (Short) Load Comple­
ment (Long)
Load Comple-
ment (Short)
Load Halfword
Load (Long) I,oad (Long) r,oad Multiple Load Negative
( Long)
Load Negative
(Short)
Load Positive (Long)
T ,oad Positive
(Short)
Load PSW Load (Short) Load (Short)
Multiply
Multiply MNEMONIC AWR
AW AUR AU N
C
CH
CL
CDR
CD
CER
CE
CVB
CVD
DR
D DP NDDR
NDD
NDER
NDE
X
EX
HDR
HER ISK L
LTDR
LTER
LCDR
LCER
LH
LDR
LD
LM
LNDR
LNER LPDR LPER LPS\V LER
LE
MR
M TYPE EXCEPTIONS CODE NOTE
RRF,C
RX,F,C
RRF,C
RXF,C
RX C
RX C
RX C
RX C
RR,F,C
RX,F,C
RR,F,C
RX,F,C S, E,LS 2E 3
A,S, E,LS 6E 3,8 S, E,LS 3E 3
A,S, E,LS 7E 3,4 A,S 54 4 A,S A,S A,S S A,S S A,S 59 4
49 2
55 4
29 3
69 3,8
39 3
79 3,4
RX A,S,D, IK 4F 8
RX SI RR
RX SS T
RRF
RXF
RRF
RXF
RX C
RX
RRF
RRF P,A,S 4E 8
M, A,S 83 S, IK ID 1
A,S, IK 5D 1,4 P,A,S,D, DK FD 5 S,U,E,FK 2D 3
A,S, U ,E,FK 6D 3,8 S,U,E,FK 3D 3 A,S,U,E,FK 7D 3,4 A,S 57 4
A,S, EX 44 2 S 24 3 S 34 3
RRZ M, A,S 09 7
RX A,S RR F,C S RR F,C S RR F,C S RRF,C
RX
RRF
RXF RS RRF,C
RRF,C
RRF,C S A,S S A,S A,S S S S RR F,C S SI L M, A,S RRF S RX FA,S
RR
RX S A,S 58 4
22 3
32 3
23 3
33 3
48 2
28 3
68 3,8
98 4
21 3
31 3 20 3 30 3
82 6,8
38 3
78 3,4
lC 1
5C 1,4
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