the protection feature is not installed and the instruc­
tion is SET STORAGE KEY or INSERT STORAGE KEY.
Privileged Operation: A LOAD PSW, SET SYSTEM MASK, SET STORAGE KEY, INSERT STORAGE KEY, WRITE DIRECT,
READ DIRECT, or DIAGNOSE is encountered while the
processor is in the problem state.
Protection: The storage key of the location desig­
nated by READ DIRECT does not match the protection
key in the psw.
Addressing: An address designates a location out­
side the available storage for the installed model.
Specification: The operand address of a LOAD psw does not have all three low-order bits zero; the operand
address of DIAGNOSE does not have as many low-order
zero bits as required for the particular CPU; the
block address specified by SET STORAGE KEY or INSERT STORAGE KEY does not have the four low-order bits aII­
zero; or the protection feature is not installed and a
psw with two nonzero protection keys is introduced.
In most of the above interruption conditions, the in­
struction is suppressed. Therefore, storage and exter­
nal signals remain unchanged, and the psw is not
changed by information from storage. The only ex­
ception is READ DIRECT, which is terminated when a
protection or addressing violation is detected. Al­
though storage remains unchanged, a timing signal
may have been made available.
When an interruption is taken, the instruction ad­
dress stored as part of the old psw has been updated
by the number of halfwords indicated by the instruc­
tion-length code in the old psw. Operand addresses are tested only when used to ad­
dress storage. The address restrictions do not apply
to the components from which an address is generated:
the content of the Dl field and the content of the
register specified by B1. Status Switching 75

I nterru ptions
The interruption system permits the CPU to change its
state as a result of conditions external to the system,
in I/O units, or in the CPU itself. The five classes of
these conditions are input; output, program, super­
visor-call, external, and machine-check interruptions.
Interruption Action An interruption consists of storing the current psw as
an old psw and fetching a new psw.
Processing resumes in the state indicated by the
new psw. The old psw contains the address of the in­
struction that would have been executed next if an
interruption had not occurred and the instruction­
length code of the last-interpreted instruction.
Interruptions are taken only when the CPU is inter­
ruptable for the interruption source. Input/output and
external interruptions may be masked by the system
mask, four of the 15 program interruptions may be
masked by the program mask, and the machine-check
interruptions may be masked by the machine-check
mask.
An interruption always takes place after one instruc­
tion interpretation is finished and before a new in­
struction interpretation is started. However, the oc­
currence of an interruption may affect the execution
of the current instruction. To permit proper program­
med action following an interruption, the cause of the
interruption is identified and provision is made to
locate the last-interpreted instruction.
When the CPU is commanded to stop, the current
instruction is finished, and all interruptions that are
pending or become pending before the end of the
instruction, and which are not masked, are taken.
The details of instruction execution, source identifi­
cation, and location determination are explained in
later sections and are summarized in the following
table.
Programming Note
A pending interruption will be taken even if the CPU becomes interruptable during only one instruction.
76 INSTRUC­ TION INTERRUPTION SOURCE JDENTlFICA TlON INTERRUPTION CODE MASK ILC EXE- PSW BITS 16-31 BITS SET CUTION Input/Output (old PSW 56, new PSW 120, priority 4)
Multiplcxor channel 00000000 aaaaaaaa 0 x complete Scledor channell 00000001 aaaaaaaa 1 x complcte Scledor channel 2 00000010 aaaaaaaa 2 x complete
Selector channel 3 00000011 aaaaaaaa 3 x complete Seledor channel 4 00000100 aaaaaaaa 4 x complete Selector channel 5 00000101 aaaaaaaa 5 x complete Scledor channel 6 00000110 aaaaaaaa 6 x completc Program (old PSW 40, new PSW 104, priority 2) Operation 0000000000000001 1,2,3
Privileged opcration 0000000000000010 1,2
Executc 0000000000000011 2 Protcction 0000000000000100 0,2,3 Addressing 00000000 00000101 1,2,3 Specification 00000000 00000110 1,2,3
Data 00000000 00000111 2,3
Fixed-point overflow 00000000 00001000 36 1,2
Fixcd-point divide 00000000 00001001 1,2
Dccimal overflow 00000000 00001010 37 3
Decimal divide 0000000000001011 3
Exponent overflow 00000000 00001100 1,2
Exponcnt underflow 00000000 000011 0 1 38 1,2 Significance 0000000000001110 39 1,2
Floating-point divide 0000000000001111 1,2
supprcss
supprcss
suppress
suppress/
terminate
suppress/
terminate
suppress
terminate
complete
suppress/
complete
complete
suppress
terminate
complcte
complete
suppress Supel'visol' Call (old PSW 32, new PSW 96, priority 2)
Instruction bits 00000000 r rr r r 1'1' r 1 complete External (old PSW 24, new PSW 88, priority 3 )
Extcrnal signal 1 00000000 xxxxxxx 1 7 x complete
External signal 2 00000000 xxxxxx1x 7 x complete
External signal 3 00000000 xxxxx lxx 7 x complete
External signal 4 00000000 xxxxlxxx 7 x complete
External signal 5 00000000 xxxlxxxx 7 x complete
External signal 6 00000000 xxlxxxxx 7 x complete
Interrupt key 00000000 xlxxxxxx 7 x complete
Timcr 00000000 lxxxxxxx 7 x complete
Machine Check (old PSW 48, new PSW 112, priority 1)
Machine malfunction 00000000 00000000 13 x terminate NOTES a Device address bits
r Bits of R, and R2 field of SUPERVIson CALL
x Unpredictable