Instruction Execution
An interruption occurs when the preceding instruction
is finished and the next instruction is not yet started.
The manner in which the preceding instruction is
finishcd may be influenced by the cause of the inter
ruption. The instruction is said to have been com
pleted, terminated, or suppressed.
In the case of instruction completion, results are
stored and the condition code is set as for normal in
struction operation, although the result may be influ
enced by the exception which has occurred.
In the case of instruction termination, all, part, or
none of the result may be stored. Therefore, the result
data are unpredictable. The setting of the condition
code, if called for, may also be unpredictable. In
general, the results should not be used for further
computation.
In the case of instruction suppression, the execution
proceeds as if no operation were specified. Results
are not stored, and the condition code is not changed.
Source Identification
The five classes of interruptions are distinguished by
the storage locations in which the old psw is stored
and from which the new psw is fetched. The detailed
causes are further distinguishcd by the interruption
code of the old psw, except for the machine-check
interruption. The bits of the interruption code are
numbered 16-31, according to their position in the psw.
For110 interruptions, additional information is pro
vided by the contents of the channel status word
stored as part of the110 interruption.
For machine-check interruptions, additional infor
mation is provided by the diagnostic procedure, which
is part of the interruption.
The following table lists the permanently allocated
main-storage locations.ADDRESS LENGTH PURPOSE a 0000 0000 Double word Initial program loading PSW 8 0000 1000 Double word Initial program loading CCW1
1600010000 Double word Initial program loading CCW2
240001 1000 Double word External old PSW 32 0010 0000 Double word Supervisor call old PSW 40 0010 1000 Double word Program old PSW 48 0011 0000 Double word Machine old PSW 56 00111000 Double word Input/output old PSW 64 0100 0000 Double word Channel status word
720100 1000 Word Channc1 address word
760100 1100 Word Unused 80 0101 0000 Word Timer
840101 0100 Word Unused
880101 1000 Double word External new PSW 96 0110 0000 Double word Supervisor call new PSW 104 0110 1000 Double word Program new PSW 112 0111 0000 Double word Machine-check new PSW 120 0111 1000 Double word Input/output new PSVV 128 1000 0000 Diagnostic scan-out areal) I)Thc size of the diagnostic scan-out mea depends on the par-
ticular model andI/O channels.
Location Determination
For some interruptions, it is desirable to locate the in
struction being interpreted when the interruption oc
curred.Since the instruction address in the old psw
designates the instruction to be executed next, it is
necessary to know the lcngth of the preceding instruc
tion. This length is recorded in bit positions 32 and
33 of the psw as the instruction-length code.
The instruction-length code is predictable only for
program and supervisor-call interruptions. For I/O
and external interruptions, the interruption is not
caused by the last-interpreted instruction, and the
code is not predictable for these instructions. For
machine-check interruptions, the setting of the code
may be affected by the malfunction and, therefore, is
unpredictable.
For the supervisor-caB interruption, the instruction
length code is 1, indicating the halfword length ofSUPERVISOR CALL. For program interruptions, the codes
1, 2, and 3 indicate the instruction length in halfwords.
The code0 is reserved for program interruptions
where the length of the instruction is not available be
cause of certain overlapping conditions in struction
fetching. Incode-O cases, the instruction address in
the old psw does not represent the next instruction
address. Instruction-length code0 can occur for a
program interruption only when the interruption is
caused by a protected or an unavailable data address.
The following table shows the states of the instruction
length code.INSTRUC- TION INSTRUC- INSTRUC- J.ENGTH psw BITS TJON INsTRUCTION TION CODE 32-33 BITS 0-1 LENGTH FORMAT a 00 Not available
101 00 One halfword RR
2 1001 Two halfwords RX
210 10 Two halfwords RS or SI 3 11 11 Three halfwords SS Programming Notes
When a program interruption is due to an incorrect
branch address, the location determined from the in
struction address and instruction-length code is the
branch address and not the location of the branch
instruction.
When an interruption occurs while theCPU is in the
wait state, the instruction-length code is always unpre
dictable.
The instructionEXECUTE represents upon interrup
tion an instruction-length code which docs not reflect
thc length of the instruction executed, but is 2, the
length of EXECUTES.
Interruptions 77
An interruption occurs when the preceding instruction
is finished and the next instruction is not yet started.
The manner in which the preceding instruction is
finishcd may be influenced by the cause of the inter
ruption. The instruction is said to have been com
pleted, terminated, or suppressed.
In the case of instruction completion, results are
stored and the condition code is set as for normal in
struction operation, although the result may be influ
enced by the exception which has occurred.
In the case of instruction termination, all, part, or
none of the result may be stored. Therefore, the result
data are unpredictable. The setting of the condition
code, if called for, may also be unpredictable. In
general, the results should not be used for further
computation.
In the case of instruction suppression, the execution
proceeds as if no operation were specified. Results
are not stored, and the condition code is not changed.
Source Identification
The five classes of interruptions are distinguished by
the storage locations in which the old psw is stored
and from which the new psw is fetched. The detailed
causes are further distinguishcd by the interruption
code of the old psw, except for the machine-check
interruption. The bits of the interruption code are
numbered 16-31, according to their position in the psw.
For
vided by the contents of the channel status word
stored as part of the
For machine-check interruptions, additional infor
mation is provided by the diagnostic procedure, which
is part of the interruption.
The following table lists the permanently allocated
main-storage locations.
16
24
72
76
84
88
ticular model and
Location Determination
For some interruptions, it is desirable to locate the in
struction being interpreted when the interruption oc
curred.
designates the instruction to be executed next, it is
necessary to know the lcngth of the preceding instruc
tion. This length is recorded in bit positions 32 and
33 of the psw as the instruction-length code.
The instruction-length code is predictable only for
program and supervisor-call interruptions. For I/O
and external interruptions, the interruption is not
caused by the last-interpreted instruction, and the
code is not predictable for these instructions. For
machine-check interruptions, the setting of the code
may be affected by the malfunction and, therefore, is
unpredictable.
For the supervisor-caB interruption, the instruction
length code is 1, indicating the halfword length of
1, 2, and 3 indicate the instruction length in halfwords.
The code
where the length of the instruction is not available be
cause of certain overlapping conditions in struction
fetching. In
the old psw does not represent the next instruction
address. Instruction-length code
program interruption only when the interruption is
caused by a protected or an unavailable data address.
The following table shows the states of the instruction
length code.
1
2 10
2
When a program interruption is due to an incorrect
branch address, the location determined from the in
struction address and instruction-length code is the
branch address and not the location of the branch
instruction.
When an interruption occurs while the
wait state, the instruction-length code is always unpre
dictable.
The instruction
tion an instruction-length code which docs not reflect
thc length of the instruction executed, but is 2, the
length of EXECUTES.
Interruptions 77