Input/Output Interruption
The 1/ () interruption provides a means by which the CPU responds to signals from I/O devices.
A request for an I/O interruption may occur at any
time, and more than one request may occur at the
same time. The requests are preserved in the I/O section until accepted by the CPU. Priority is estab­
lished among requests so that only one interruption
request is processed at a time.
An I/O interruption can occur only after execution
of the current instruction is completed and while the CPU is interruptable for the channel presenting the
request. Channels are masked by system mask bits 0-6. Interruptions masked off remain pending.
The I/O interruption causes the old psw to be stored
at location 56 and causes the channel status word as­
sociated with the interruption to be stored at location
64. Subsequently, a new psw is loaded from location 120. The interruption code in the old psw identifies the
channel and device causing the interruption in bits
21-23 and 24-31, respectively. Bits 16-20 of the old psw
are made zero. The instruction-length code is unpre­
dictable.
Program Interruption
Exceptions resulting from improper specification or
use of instructions and data cause a program interrup­
tion.
The current instruction is completed, terminated, or
suppressed. Only one program interruption occurs for
a given instruction and is identified in the old psw.
The occurrence of a program interruption docs not
preclude the simultaneous occurrence of other pro­
gram-interruption causes. Which of several causes is
identified may vary from one occasion to the next and
from one model to another.
A program interruption can occur only when the
corresponding mask bit, if any, is one. When the mask
bit is zero, the interruption is ignored. Program inter­
ruptions do not remain pending. Program mask bits
36-39 permit masking of four of the 15 interruption
causes.
The program interruption causes the old psw to be
stored at location 40 and a new psw to be fetched
from location 104. The cause of the interruption is identified by inter­
ruption-code bits 28-31. The remainder of the interrup­
tion code, bits 16-27 of the PSW, are made zero. The
instruction-length code indicates the length of the
preceding instruction in halfwords. For a few cases,
78
the instruction length is not available. These cases are
indicated by code O. A description of the individual program exceptions
follows. The application of these rules to each class of
instructions is further described in the applicable sec­
tions. Some of the exceptions listed may also occur in
operations executed by I/O channels. In that event, the
exception is indicated in the channel status word
stored with the I/O interruption (as explained under "Input/Output Operations"). Operation Exception
When an operation code is not assigned or the as­
signed operation is not available on the particular
model, an operation exception is recognized. The op­
eration is suppressed.
The instruction-length code is 1, 2, or 3.
Privileged-Operation Exception
When a privileged instruction is encountered in the
problem state, a privileged-operation exception is rec­
ognized. The operation is suppressed.
The instruction-length code is 1 or 2.
Execute Exception
When the subject instruction of EXECUTE is another
EXECUTE, an execute exception is recognized. The
operation is suppressed.
The instruction-length code is 2.
Protection Exception
When the storage key of a result location does not
match the protection key in the PSW, a protection ex­
ception is recognized.
The operation is suppressed, except in the case of STORE MULTIPLY, READ DIRECT, and variable-length op­
erations, which are terminated.
The instruction-length code is 0, 2, or 3.
Addressing Exception
When an address specifies any part of data, an in­
struction, or a control word outside the available
storage for the particular installation, an addressing
exception is recognized.
The operation is terminated for an invalid data
address. Data in storage remain unchanged, except
when designated by valid addresses. The operation is
suppressed for an invalid instruction address.
The instruction-length code normally is 1, 2 or 3;
but may be 0 in the case of a data address.

Specification Exception
A specification exception is recognized when:
1. A data, instruction, or control-word address does
not specify an integral boundary for the unit of in­
formation.
2. The Rl field of an instruction specifies an odd
register address for a pair of general registers that
contains a 64-bit operand.
3. A floating-point register address other than 0, 2,
4, or 6 is specified.
4. The multiplier or divisor in decimal arithmetic
exceeds 15 digits and sign.
5. The first operand field is shorter than or equal to
the second operand field in decimal multiplication or
division.
6. The block address specified in SET STORAGE KEY or
INSERT STORAGE KEY has the four low-order bits not
all zero.
7. A psw with nonzero protection key is loaded
and the protection feature is not installed.
The operation is suppressed. The instruction-length
code is 1, 2, or 3.
Data Exception
A data exception is recognized when:
1. The sign or digit codes of operands in decimal
arithmetic or editing operations or in CONVERT TO BINARY are incorrect.
2. Fields in decimal arithmetic overlap incorrectly.
3. The decimal multiplicand has too many high­
order significant digits.
The operation is terminated. The instruction-length
code is 2 or 3.
Fixed-Point-Overflow Exception
When a high-order carry occurs or high-order signifi­
cant bits are lost in fixed-point add, subtract, shift, or
sign-control operations, a fixed-point-overflow excep­
tion is recognized.
The operation is completed by ignoring the infor­
mation placed outside the register. The interruption
may be masked by psw bit 36.
The instruction-length code is 1 or 2.
Fixed-Point-Divide Exception
A fixed-point-divide exception is recognized when a
quotient exceeds the register size in fixed-pOint divi­
sion, including division by zero, or the result of CON­ VERT TO BINARY exceeds 31 bits.
Division is suppressed. Conversion is completed by
ignoring the information placed outside the register.
The instruction-length code is 1 or 2. Decimal-Overflow Exception
When the destination field is too small to contain the
result field in a decimal operation, a decimal-overflow
exception is recognized.
The operation is completed by ignoring the overflow
information. The interruption may be masked by psw
bit 37.
The instruction-length code is 3.
Decimal-Divide Exception
When a quotient exceeds the specified data field
size, a decimal-divide exception is recognized. The
operation is suppressed.
The instruction-length code is 3.
Exponent-Overflow Exception
When the result characteristic exceeds 127 in floating­
point addition, subtraction, multiplication, or division,
an exponent-overflow exception is recognized. The
operation is terminated.
The instruction-length code is 1 or 2. Exponent-U nderflow Exception
When the result characteristic is less than zero in
floating-point addition, subtraction, multiplication, or
division, an exponent-underflow exception is rec­
ognized.
The operation is completed by making the result a
true zero. The interruption may be masked by psw
bit 38.
The instruction-length code is 1 or 2.
Significance Exception
When the result of a floating-point addition or sub­
traction has an all-zero fraction, a significance excep­
tion is recognized.
The operation is completed. The interruption may
be masked by psw bit 39. The manner in which the
operation is completed is determined by the mask bit.
The instruction-length code is 1 or 2.
Floating-Point-Divide Exception
When division by a floating-point number with zero
fraction is attempted, a floating-point divide exception
is recognized. The operation is suppressed.
The instruction-length code is 1 or 2.
Supervisor-Col/Interruption
The supervisor-call interruption occurs as a result of
the execution of SUPEHVISOR CALL.
The supervisor-call interruption causes the old psw
to be stored at location 32 and a new psw to be
fetched from location 96.
Interruptions 79