The contents of bit positions 8-15 of the SUPERVISOR CALL become bits 24-31 in the interruption code of the
old psw. Bits 16-23 of the interruption code are made
zero. The instruction-length code is 1, indicating the
halfword length ofSUPERVISOR CALL. Programming Notes
The name"supervisor call" indicates that one of the
majorpurposes of the interruption is the switching
from problem to supervisor state. This major purpose
does not preclude the use of this interruption for other
types of status-switching.
The jnterruption code may be used to convey a
message from the calling program to the supervisor.
WhenSUPERVISOR CALL is performed as the subject
instruction ofEXECUTE, the instruction-length code is 2.
External Interruption
The external interruption provides a means by which
theCPU responds to signals from the timer, from the
interrupt key, and from external units.
A request for an external interruption may occur at
any time, and requests from diHerent sources may
occur at the same time. Requests are preserved until
honored by theCPU. All pending requests are pre
sented simultaneously when an external interruption
occurs. Each request is presented only once. When
several requests from one source are made before the
interruption is taken, only one interruption occurs.
An external interruption can occur only when sys
tem mask bit 7 is one and after execution of the cur
rent instruction is completed. The interruption causes
the old psw to be stored at location 24 and a new
psw to be fetched from location 88.
The source of the interruption is identified by inter
ruption-code bits 24-31. The remainder of the interrup
tion code, psw bits 16-23, is made zero. The instruc
tion-length code is unpredictable for external inter
ruptions.
Timer
A timer value changing from positive to negative
causes an external interruption with bit 24 of the in
terruption code turned on.
Timer111111111 23 24 25 26 27 28 29 30 31
The timer occupies a 32-bit word at storage location
80. In the standard form, the contents of the timer are
reduced by a one in bit position 21 and in bit position80 23 every 1/60th of a second or the timer contents are
reduced by one in bit position 21 and in bit position 22
every 1/50th of a second. The choice is determined by
the available line frequency. The gross result in either
case is equivalent to reducing the timer by one in bit
position 23 every 1/300th of a second.
Higher resolution may be obtained in some models
by counting with higher frequency in one of the posi
tions 24 through 31. In each case, the frequency is ad
justed to give counting at300 cycles per second in bit
23, as shown in the table. The full cycle of the timer
is 15.5 hours.
BITPOSITION FREQUENCY RESOLUTION 23 300 cps 3.33 ms
24600 cps 1.67 ms
25 1.2 kc 833fLS 26 2.4 kc 417 fLS 27 4.8 kc 208 fLS 28 9.6 kc 104 fLS 29 19.2 kc 52 fLS 30 38.4 kc 26 fLS 31 76.8 kc . 13 fLS The count is treated as a signed integer by following
the rules forfixed-pOint arithmetic. The negative over
flow, occurring as the timer is counted from a large
negative number to a large positive number, is ig
nored. The interruption is initiated as the count pro
ceeds from a positive number, including zero, to a
negative number.
The timer is updated whenever access to storage
permits. An updated timer value is normally available
at the end of each instruction execution; thus, a real
time count can be maintained. Timer updating may he
omitted whenI/O data transmission approaches the
limit of storage capability and when the instruction
time forREAD DIRECT is excessive.
After an interruption is initiated, the timer may
have been updated several times before theCPU is
actually interrupted, depending upon instruction exe
cution time.
The timer remains unchanged when theCPU is in
the stopped state or when the rate switch on the
operator intervention panel is set toINSTRUCTION STEP. The timer value may be changed at any time by
storing a new value in storage location80 (except
when this location is protected).
The timer is an optional feature on some models.
Programming Note
The timer in association with a program can serve both
as a real-time clock and as an interval timer.Interrupt Key
Pressing the interrupt key on the operator control
section of the system control panel causes an external
old psw. Bits 16-23 of the interruption code are made
zero. The instruction-length code is 1, indicating the
halfword length of
The name
major
from problem to supervisor state. This major purpose
does not preclude the use of this interruption for other
types of status-switching.
The jnterruption code may be used to convey a
message from the calling program to the supervisor.
When
instruction of
External Interruption
The external interruption provides a means by which
the
interrupt key, and from external units.
A request for an external interruption may occur at
any time, and requests from diHerent sources may
occur at the same time. Requests are preserved until
honored by the
sented simultaneously when an external interruption
occurs. Each request is presented only once. When
several requests from one source are made before the
interruption is taken, only one interruption occurs.
An external interruption can occur only when sys
tem mask bit 7 is one and after execution of the cur
rent instruction is completed. The interruption causes
the old psw to be stored at location 24 and a new
psw to be fetched from location 88.
The source of the interruption is identified by inter
ruption-code bits 24-31. The remainder of the interrup
tion code, psw bits 16-23, is made zero. The instruc
tion-length code is unpredictable for external inter
ruptions.
Timer
A timer value changing from positive to negative
causes an external interruption with bit 24 of the in
terruption code turned on.
Timer
The timer occupies a 32-bit word at storage location
80. In the standard form, the contents of the timer are
reduced by a one in bit position 21 and in bit position
reduced by one in bit position 21 and in bit position 22
every 1/50th of a second. The choice is determined by
the available line frequency. The gross result in either
case is equivalent to reducing the timer by one in bit
position 23 every 1/300th of a second.
Higher resolution may be obtained in some models
by counting with higher frequency in one of the posi
tions 24 through 31. In each case, the frequency is ad
justed to give counting at
23, as shown in the table. The full cycle of the timer
is 15.5 hours.
BIT
24
25 1.2 kc 833
the rules for
flow, occurring as the timer is counted from a large
negative number to a large positive number, is ig
nored. The interruption is initiated as the count pro
ceeds from a positive number, including zero, to a
negative number.
The timer is updated whenever access to storage
permits. An updated timer value is normally available
at the end of each instruction execution; thus, a real
time count can be maintained. Timer updating may he
omitted when
limit of storage capability and when the instruction
time for
After an interruption is initiated, the timer may
have been updated several times before the
actually interrupted, depending upon instruction exe
cution time.
The timer remains unchanged when the
the stopped state or when the rate switch on the
operator intervention panel is set to
storing a new value in storage location
when this location is protected).
The timer is an optional feature on some models.
Programming Note
The timer in association with a program can serve both
as a real-time clock and as an interval timer.
Pressing the interrupt key on the operator control
section of the system control panel causes an external