trol unit contains a pending channel end or control
unit end for the addressed device. The csw unit­
status field contains the busy bit, identifies the inter­
ruption condition, and may contain other bits pro­
vided by the device or control unit. The interruption
condition is cleared. The channel-status field contains
zeros.
3. The I/O device or the control unit is executing a
previously initiated operation, or the control unit has
pending channel end or control unit end for a device
other than the one addressed. The csw unit-status
field contains the busy bit or, if the control unit is
busy, the busy and status-modifier bits. The channel­
status field contains zeros.
4. The I/O device or channel detected an equip­
ment or programming error during execution of the
instruction. The channel-end and busy bits are off,
unless the error was detected after the device was
selected and was found to be busy, in which case the
busy bit, as well as any bits indicating pending inter­
ruption conditions, are on. The interruption conditions
indicated in the csw have been cleared at the device.
The csw identifies the error condition. The I/O op­
eration has not been initiated. No interruption condi­
tions are generated at the I/O device or subchannel.
Resulting Condition Code:
o I/O operation initiated and channel proceed-
ing with its execution
1 csw stored
2 Channel or sub channel busy
3 Not operational Program Interruptions: Privileged operation.
Programming Note
When a programming error occurs and the addressed
device contains an interruption condition, with the
channel and subchannel in the available state, START I/O mayor may not clear the interruption condition,
depending on the type of error and the model. If the
instruction has caused the device to be interrogated,
as indicated by the presence of the busy bit in the
csw, the interruption condition has been cleared, and
the csw contains program check, as well as the status
from the device.
Test I/O rio 51
9D 78 1516 1920 31
The state of the addressed channel, subchannel, and
device is indicated by setting the condition code in
the psw and, under certain conditions, by storing the
csw. Pending interruption conditions may be cleared.
The instruction TEST I/O is executed only when the CPU is in the supervisor state.
Bit positions 21-31 of the sum formed by the addi­
tion of the content of register Bl and the content of
the Dl field identify the channel, subchannel, and I/O device to which the instruction applies.
When any of the following conditions is detected, TEST I/O causes the csw at location 64 to be stored.
The content of the csw pertains to the I/O device ad­
dressed by the instruction.
1. The subchannel contains a pending interruption
condition due to a terminated operation at the ad­
dressed device. The interruption condition is cleared.
The protection key, command address, and count
fields contain the final values for the I/O operation,
and the status may include other bits provided by
the channel and the device. The interruption condi­
tion in the subchannel is not cleared, and the csw is
not stored if the interruption condition is associated
with an operation on a device other than the one
addressed.
2. The I/O device contains a pending interruption
condition due to device end or attention, or the con­
trol unit contains a pending channel end or control
unit end for the addressed device. The csw unit-status
field identifies the interruption condition and may
contain other bits provided by the device or control
unit. The interruption condition is cleared. The busy
bit in the csw is off. The other fields of the csw con­
tain zeros.
3. The I/O device or the control unit is executing a
previously initiated operation or the control unit has
pending channel end or control unit end for a device
other than the one addressed. The csw unit-status
field contains the busy bit or, if the control unit is
busy, the busy and status-modifier bits. Other fields
of the csw contain zeros.
4. The I/O device or channel detected an equip­
ment error during execution of the instruction. The
csw identifies the error condition. No interruption
conditions are generated at the I/O device or the sub­
channel.
When TEST I/O is used to clear an interruption con­
dition from the subchannel and the channel has not
yet accepted the condition from the device, the in­
struction causes the device to be selected and the
interruption condition in the device to be reset. Dur­
ing certain I/O operations, some types of devices can­
not provide their current status in response to TEST I/O. The tape control unit, for example, is in such a
state when it has provided the channel-end condition
and is executing the backspace-file operation. When TEST I/O is issued to a control unit in such a state, the
unit-status field of the csw contains the busy and Input/Output Operations 93
status-modifier bits, with zeros in the other csw fields.
The interruption condition in the device and in the
subchannel is not cleared. On some types of devices, such as the 2702 Trans­
mission Control, the device never provides its current
status in response to TEST I/O, and an interruption
condition can be cleared only by permitting an I/O interruption. When TEST I/O is issued to such a device,
the unit-status field contains the status-modifier bit.
The interruption condition in the device and in the
subchannel, if any, is not cleared.
However, at the time the channel assigns the high­
est priority for interruptions to a condition associated
with an operation at the subchannel, the channel ac­
cepts the status from the device and clears the cor­
responding condition at the device. When TEST I/O is addressed to a device for which the channel has
already accepted the interruption condition, the de­
vice is not selected, and the condition in the subchan­
nel is cleared regardless of the type of device and its
present state. The csw contains unit status and other
information associated with the interruption condi­
tion.
Resulting Condition Code:
o Available
1 csw stored
2 Channel or subchannel busy
3 Not operational
Program Interruptions: Privileged operation.
Programming Notes
Masking of channels provides the program a means of
controlling the priority of I/O interruptions selectively
by channels. The priority of devices attached on a
channel is fixed and cannot be controlled by the pro­
gram. The instruction TEST I/O permits the program to
clear interruption conditions selectively by I/O device.
When a csw is stored by TEST I/O, the interface­
control-check and channel-control-check indications
may be due to a condition already existing in the
channel or due to a condition created by TEST I/O. Similarly, presence of the unit-check bit in the ab­
sence of channel-end, control-unit-end or device-end
bits may be due to either a condition created by the
preceding operation or an equipment error detected
during the execution of TEST I/O. Halt I/O HIO 51
9E 78 1516 1920 31
Execution of the current I/O operation at the address­
ed sub channel or channel is terminated. The subse-
94
quent state of the subchannel depends on the type of
channel. The csw may be stored. The instruction HALT I/O is executed only when the CPU is in the supervisor
state.
Bit positions 21-31 of the sum formed by the addi­
tion of the content of register Bl and the content of
the Dl field identify the I/O device to whose subchan­
nel or channel the instruction applies.
When HALT I/O is issued to a channel operating in
the burst mode, data transfer for the burst operation
is terminated and the device performing the burst
operation is immediately disconnected from the chan­
nel. The subchannel and I/O device address in the in­
struction is ignored. When the instruction is issued to
the multiplexor channel operating in the multiplex
mode and the addressed subchannel is working, data
transfer for the current operation on the subchannel
is terminated. In this case the channel uses the device
address appearing in the instruction to identify the
subchanncl and select the device on the I/O interface.
The address of the device on the subchannel is not
significant, providing the control unit responds to the
address.
The termination of an operation by HALT I/O on the
selector channel causes the channel and su bchannel to
be placed in the interruption-pending state. The in­
terruption condition is generated without receiving
the channel-end signal from the device. When HALT I/O causes an operation on the multiplexor channel to
be terminated, the subchannel remains in the working
state until the device provides the next status byte,
whereupon the subchannel is placed in the interrup­
tion-pending state.
The control unit associated with the terminated
operation remains unavailable for a new I/O operation
until the data-handling portion of the operation in
the control unit is terminated, whereupon it generates
the channel-end condition. Channel end may be gen­
erated at the normal time for the operation, earlier,
or later, depending upon the operation and type of
device. The I/O device executing the terminated oper­
ation remains in ,the working state until termination
of the inherent cycle of the operation, at which time
device end is generated. If blocks of data at the de­
vice are defined, such as reading on magnetic tape,
the recording medium is advanced to the beginning of
the next block.
If the control unit is shared, all devices attached to
the control unit appear in the working state until the
channel-end condition is accepted by the CPU. The
states of the other devices, however, are not perma­
nently affected. Operations such as rewinding mag­
netic tape or positioning a disk access mechanism are
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