order byte. Operand fields may be located on any
byte boundary, and may have length up to 31 digits
and sign. Operands participating in an operation have
independent lengths. Packing of digits within a byte
(Figure 8) and of variable-length fields within stor­ age results in efficient use of storage, in increased
arithmetic performance, and in an improved rate of
data transmission between storage and files. I Digit I Digit I Digit Digit I Digit I Digit I Digit I Sign I I Zone I Digit I Zone C-_- Digit I Zone I Digit I Sign I Digit I Figure 8. Packed and Zoned Decimal Number Formats
Decimal numbers may also appear in a zoned for­ mat as a subset of the eight-bit alphameric character
set (Figure 8). This representation is required for
character-set sensitive I/O devices. The zoned format
is not used in decimal arithmetic operations. Instruc­ tions are provided for packing and unpacking decimal
numbers so that they may be changed from the zoned
to the packed format and vice versa.
Floating-Point Arithmetic
Floating-point numbers occur in either of two fixed­ length formats -short or long. These formats differ
only in the length of the fractions (Figure 9).
Short Floating-Point Number IS I Characteristic I Fraction
o I 7 8 31
Long Floating-Point Number _________ F_ra_c_ti_o_n ______ ______ o 1 78 63
Figure 9. Short and Long Floating-Point Number Formats Operands are either 32 or 64 bits long. The short
length, equivalent to seven decimal places of pre­ cision, permits a maximum number of operands to be
placed in storage and gives the shortest execution
times. The long length, used when higher precision is
desired, gives up to 17 decimal places of precision,
thus eliminating most requirements for double-pre­ cision arithmetic.
The operand lengths, being powers of two, permit
maximum efficiency in the use of binary addressing
and in matching the phys,ical word sizes of storage.
Floating-point arithmetic is designed to allow easy
transition between the two formats.
The fraction of a floating-point number is expressed
in hexadecimal ( base 16) digits, each consisting of
four binary bits and having the values 0-15. In the
short format, the fraction consists of six hexadecimal
digits occupying bits 8-31. In the long format the
fraction has 14 hexadecimal digits occupying bits 8-63.
The radix point of the fraction is assumed to be im­ mediately to the left of the high-order fraction digit.
To provide the proper magnitude for the floating­ point number, the fraction is considered to be mul­ tiplied by a power of 16. The characteristic portion,
bits 1-7 of both formats, is used to indicate this power.
The characteristic is treated as an excess 64 number
with a range from -64 through +63, and permits
representation of decimal numbers with magnitudes
in the range of 10-
to 10
Bit position 0 in either format is the sign (S) of the
fraction. The fraction of negative numbers is carried
in true form.
Four 64-bit floating-point registers are provided.
Arithmetic operations are performed with one oper­ and in a register and another either in a .register or
from storage. The result, developed in a register, is
generally of the same length as the operands. The
availability of several floating-point registers elimi­ nates much storing and loading of intermediate re­ sults. Logical Operations
Logical information is handled as fixed-length and
variable-length data. It is subject to such operations as
comparison, translation, editing, bit testing, and bit
When used as a fixed-length operand, logical in­ formation can consist of either one, four, or eight
bytes and is processed in the general registers.
A large portion of logical information consists of
alphabetic or numeric character codes, called alpha­ meric data, and is used for communication with char­ acter-set sensitive I/O devices. This information has
the variable-field-Iength format and can consist of up
to 256 bytes (Figure 10). It is processed in storage,
left to right, an eight-bit byte at a time.
The CPU can handle any eight-bit character set, al­ though certain restrictions are assumed in the decimal
arithmetic and editing operations. However, all char­ acter-set sensitive I/O equipment will assume either
the extended binary-coded-decimal interchange code
System Structure 11
Fixed Lengl'h Logical Information I Logical Data Variable-Length Logical Information I Character I Character 16 Character Figure 10. Fixed-Length and Variable-Length Logical
( EBCDIC) (Figure 11) or the American Standard Code for Information Interchange (ASCII) extcnded to eight
bits (Figure 12).
The preferred codes do not have a graphic defined
for all 256 eight-bit codes. When it is desirable to rep­
resent all possible bit patterns, a hexadecimal repre­
sentation may be used instead of the preferred eight­
bit code. The hexadecimal representation uses one
graphic for a four-bit code, and therefore, two graph­
ics for an eight-bit byte. The graphics 0-9 are used
for codes 0000-1001; the graphics A-F are used for
codes 1010-1111. Bit Positions -,----. .. 01 L U:-
4567 00 01 10 11 00 01 10 11 0000 NUL BLANK & - 0001 / 0010 0011 0100 PF RES BYP PN 0101 HT NL LF RS 0110 LC .BS EOB UC - 0111 DEL IDL PRE EOT 1000 -- 1001 , " 1010 ? ! : 1011 $ ,
# 1100 4--- * % @ 1101 ( ) ry-.. I 1110 + ;
1111 $ C7 +
Figure 11. Extended Binary-Coded-Decimal Interchange Code 12
Program Execution
The CPU program consists of instructions, index words,
and control words specifying the operations to be per­
formed. This information resides in main storage and
general registers, and may be operated upon as data. Instruction Format
The length of an instruction format can be one, two,
or three halfwords. It is related to the number of stor­
age addresses necessary for the operation. An instruc­
tion consisting of only one halfword causes no refer­
ence to main storage. A two-halfword instruction pro­
vides one storage-address specification; a three-half­
word instruction provides two storage-address specifi­
cations. All instructions must be located in storage on
integral boundaries for halfwords. Figure 13 shows
five basic instruction formats.
The five basic instruction formats are denoted by
the format codes RR, RX, RS, SI, and ss. The format
codes express, in general terms, the operation to be
performed. RR denotes a register-to-register operation;
RX, a register-to-indexed-storage operation; RS, a regis- 00 01 10 11 00 01 10 11 > < :j: 0 a
A J 1
b k s B K S 2
c I t C L T 3
d m u D
e n v E N V 5
f 0 w F 0 W 6
9 P x G P X 7
h q y H
Q Y 8
i r z I R Z 9 1----- _._---
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