Interruption Handling I/O Interrupts Input/output interrupts from completed I/O operations initiate various
completion routines and the scheduling of further I/O requests. The I/O interrupt handling routine also gathers device sense information.
Program Interrupt Program interrupts can occur in two states. If the processor is in
supervisor state, the interrupt indicates a system failure in the CP nucleus and causes the system to abnormally terminate. If the processor
is in problem state, a virtual machine is executing. CP takes control
to perform any required paging operations to satisfy the exception, or
to simulate the instruction. The fault is transparent to the virtual
machine execution. Any other program interruFt is a result of the
virtual machine processing and is reflected to the machine for handling.
Machine Check Interrupt When a machine check occurs, the CP Recovery Management Support (RMS) gains control to save data associated with the failure for the Field
Engineer. RMS analyzes the failure to determine the extent of damage.
Damage assessment results in one of the following actions being
taken: System termination (CP disabled wait state) Attached processor disabled (system continues in uniprocessor mode) Selective virtual user termination Selective virtual machine reset Refreshing of
damaged information with no effect on system Refreshing of damaged information with the defective storage page
removed from further system use Error recording only for certain soft machine checks
The system operator is informed of all actions taken by the RMS routines. When a machine check occurs during VM/370 startup (before the
system is sufficiently initialized to permit RMS to operate
successfully), the processor goes into a disabled wait state and places
a completion code of X'OOB' in the leftmost bytes of the current PSi. 86 IBM 7n/37C Sy£tem Programmeris Guide
SVC Interrupt When an SVC interrupt occurs, the SVC interrupt routine is entered. If
the machine is in problem mode, the type of interrupt (if it is other
than an SVC 76 or ADSTOP SVC) is reflected to the pseudo-supervisor
(that is, the supervisor operating in user's virtual machine). Control is transferred to the appropriate interrupt handler for IDSTOP SVCs and all SVC 76s.
If the machine
determined, and a
is in supervisor mode,
branch is taken to the
External Interrupt
the SVC interrupt code is aPFropriate SVC interrupt
If a timer interrupt occurs, CP processes it according to type. The
interval timer indicates time slice end for the running user. The clock
comparator indicates that a specified timer event occurred, such as
midnight, scheduled shutdown, or user event reached.
The external console interrupt invokes CP processing to switch from
the 3210 or 3215 to an alternate operator's console.
Synchronous Interrupts In an Attached Processor System Generally, when synchronous interrupts (such as program and SVC interrupts) occur in an attached processor system, the first-level
interrupt handler (FLIH) atte.pts to gain the system lock before
proceeding. If it is already in use, the interrupt status is stacked
and deferred. The interrupted processor then attempts to run a user. Real I/O Interrupts
In an attached processor configuration. only the main processor can
receive real 1/0 interrupts. To ensure this, the channel masks in
control register 2 on the main processor are initialized to ones to
enable for interrupts fro. any available channel. On the attached
processor, the channel masks in control register 2 are initialized to
Part 2. Control program (CP) 87
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