status Bits Various status conditions are defined
whereby the issuing and addressed CPUs can indicate their responses to the
specified order. The status conditions
and their bit positions in the general
register designated by the R, field of
the SIGNAL PROCESSOR instruction are
shown in the figure "Status Conditions." Bit Position Status Condition 0 Equipment check
1-23 Unassigned; zeros stored
24 External-call pending
25 Stopped
26 Operator intervening
27 Check stop
28 Not ready
29 Inoperative 30 Invalid order
31 Receiver check
Status Conditions The status condition assigned to bit
position 0 is generated by the CPU executing SIGNAL PROCESSOR. The remain­ ing status conditions are generated by
the addressed CPU. When the equipment-check condition
exists, bit 0 of the general register
designated by the R, field of the SIGNAL PROCESSOR instruction is set to one,
unassigned bits of the status register
are set to zeros, and the contents of
other status bits are unpredictable. In
this case, condition code 1 is set inde­
pendent of whether the access path to
the addressed CPU is busy and independ­ ent of whether the addressed CPU is not
operational, is busy, or has presented
zero status.
When the access path to the addressed CPU is not busy and the addressed CPU is
operational and does not indicate busy
to the currently specified order, the addressed CPU presents its status to the issuing CPU. These status bits are of
two types:
1. Status bits 24-29 indicate the
presence of the corresponding
conditions in the addressed CPU at the time the order code is
received. Except in response to
the sense order, each condition is
indicated only when the condition
precludes the successful execution
of the specified order. In the
case of sense, all existing status
conditions are indicated; the
operator-intervening and not-ready
conditions each are indicated if
these conditions preclude the
execution of any installed order.
2. Status bits 30 and 31 indicate that
the corresponding conditions were
detected by the addressed CPU during reception of the order.
If the presented status is all zeros,
the addressed CPU has accepted the
order, and condition code 0 is set at
the issuing CPU; if the presented status
is not all zeros, the order has been
rejected, the status is stored at the
issuing CPU in the general register
designated by the R, field of the SIGNAL PROCESSOR instruction, zeros are stored
in the unassigned bit positions of the
register, and condition code 1 is set.
The status conditions are defined as
follows: EgLdpment Check: This condition exists
when the CPU executing the instruction
detects equipment malfunctioning that
has affected only the execution of this
instruction and the associated order.
The order code mayor may not have been
transmitted and mayor may not have been
accepted, and the status bits provided
by the addressed CPU may be in error.
External Call Pending: This condition
exists when an external-call inter­
ruption condition is pending in the
addressed CPU because of a previously
issued SIGNAL PROCESSOR order. The
condition exists from the time an
external-call order is accepted until
the resultant external interruption has been completed or a CPU reset occurs.
The condition may be due to the issuing CPU or another CPU. The condition, when
present, is indicated only in response
to sense and to external call.
Stopped: This condition exists when the
addressed CPU is in the stopped state.
The condition, when present, is indi­
cated only in response to sense. This
condition cannot be reported as a result
of a SIGNAL PROCESSOR by a CPU address­
ing itself. Operator Intervening: This condition exists when the addressed CPU is execut­
ing certain operations initiated local or remote operator facilities.
The particular manually initiated oper­
ations that cause this condition to be
present depend on the model and on the
order specified. On machines which do
not implement the IML order, the condi­
tions described under "Not Ready" may be indicated as an operator-intervening
condition. The operator-intervening
condition, when present, can be indi­ cated in response to all orders. Operator i nterven i ng is i ndi cated in
response to sense if the condition is
present and precludes the acceptance of
any of the installed orders. The condi­
tion may also be indicated in response Chapter 4. Control 4-41

to unassigned or uninstalled orders.
This condition cannot arise as a result
of a SIGNAL PROCESSOR by a CPU address­
ing itself. Check Stop: This condition exists when
the addressed CPU is in the check-stop
state. The condition, when present, is
indicated only in response to sense,
external call, emergency signal, start,
stop, restart, and stop and sto re
status. The condition may also be indi­
cated in response to unassigned or
uninstalled orders. This condition
cannot be reported as a result of a SIGNAL PROCESSOR by a CPU addressing
itself.
Not Ready: This condition exists when
the addressed CPU uses reloadable
control storage to perform an order and
the required microprogram is not loaded.
The not-ready condition may be indicated
in response to all orders except IMl.
This condition cannot arise as a result
of a SIGNAL PROCESSOR by a CPU address­
ing itself.
Inoperative: This condition indicates
that the execution of the operation
specified by the order code requires the use of a service processor which is
inoperative. The failure of the service
processor may have been previously reported by a service-processor-damage
machine-check condition. The inopera­
tive condition cannot occur for the
sense, external-call, or emergency­
signal order code.
Invalid Order: This condition exists
during associated
with the execution of SIGHAL PROCESSOR when an unassigned or uninstalled order code is decoded. Receiver Check: This condition exists when the addressed CPU detects malfunc­
tioning of equipment during the communi­
cations associated with the execution of SIGNAL PROCESSOR. When this condition
is indicated, the order has not been
initiated, and, since the malfunction
may have affected the generation of the
remaining receiver status bits, these bits are not necessarily valid. A
machine-check condition mayor may not
have been generated at the addressed CPU. The following chart summarizes status conditions are presented issuing CPU in response to each
code.
which
to the
order
4-42 System/370 Principles of Operation Status Condition 31 Receiver 30 Invalid order
29 Inoperative 28 Not ready
27 Check stop intervening" m 24 External call pend. l Order Sense
External call
Emergency signal
Start
stop
Restart
Initial program reset Program reset
Stop and store status IMl* Initial CPU reset* CPU reset* Unassigned order
Explanation: -V -V -V X X X
X 0 X
o 0 X
o 0 X
o 0 X
o 0 X
o 0 X
o 0 X
o 0 X
o 0 X
o 0 X
o 0 X
o 0 X -V '" X X
X X
X X
X X
X X
X X
o X
o X
X X
o 0 o X
o X
E X -V -V -V o 0 X
o 0 X
o 0 X
X 0 X
X 0 X
X 0 X
X 0 X
X 0 X
X 0 X
X 0 X
X 0 X
X 0 X
X 1 X n The current state of the operator­
intervening condition may depend on
the order code that is being inter­
preted. If a one is presented in the
receiver-check bit position, the
values presented in the other bit
positions are not necessarily
valid. * If the order code is implemented, use the line entry for the order
code; if the order code is not
implemented, use the line entry
labeled "Unassigned Order." o A zero is presented in this bit
position regardless of the current
state of this condition.
1 A one is presented in this bit
position.
X A zero or a one is presented in
this bit position, reflecting the
current state of the corresponding
condition.
E Either a zero or the current state
of the corresponding condition is
indicated.
If the presented status bits are all
zeros, the order has been accepted, and
the issuing CPU sets condition code O. If one or more ones are presented, the
order has been rejected, and the issuing CPU stores the status in the general register designated by the R, field of • the SIGNAL PROCESSOR instruction and sets condition code 1.