The instruction-length code is 0, 1, 2,
or 3. Code 0 is set only if a specifi­
cation exception is indicated concur­
rently.
The PER event is indicated by setting
bit 8 of the program-interruption code
to one. See the section "Program-Event Recording" in Chapter 4, "Control," for
a detailed description of the PER event
and the associated interruption informa­
tion. Primary-Authority Exception
A primary-authority exception is recog­
nized during ASH authorization in PROGRAM TRANSFER with space switching (PT-ss) when either:
1. The authority-table entry indicated by the authorization index in
control register 4 is beyond the
length of the authority table
designated by the ASN-second-table entry.
2. The primary-authority bit indicated
by the authorization index is zero.
The ASH being translated is stored at
real locations 146-147, and real
locations 144-145 are set to zeros.
The operation is nullified.
The instruction-length code is 2.
The primary-authority exception is indi­
cated by a program-interruption code of 0024 hex (or OOA4 hex if a concurrent PER event is indicated). Privileged-Operation Exception
A privileged-operation exception is
recognized when any of the following is
true:
1. Execution of a privileged instruc­
tion is attempted in tha problem
state.
2. The value of the rightmost bit of the general register designated by
the R2 field of the PROGRAM TRANS­ FER instruction is zero and would cause the PSW bit to
change from the problem state (one)
to the supervisor 5tate (zero). 3. In the problem state, the key value
specified by the second operand of
the SET PSW KEY FROM ADDRESS instruction corresponds to a zero PSW-key-mask bit in control regis­
ter 3.
4. In the problem state, the key value
specified by the rightmost byte of
the register designated by the R3 field of the MOVE WITH KEY instruc­
tion corresponds to a zero PSW­ key-mask bit in control register 3.
5. In the problem state, the key value
specified by the rightmost byte of
the register designated by the R3 field of the instructions MOVE TO PRIMARY and MOVE TO SECONDARY corresponds to a zero PSW-key-mask bit in control register 3.
6. In the problem state, any of the
instructions
EXTRACT PRIMARY ASN EXTRACT SECONDARY ASH INSERT ADDRESS SPACE CONTROL INSERT PSW KEY INSERT VIRTUAL STORAGE KEY is encountered, and the
extraction-authority control, bit 4
of control register 0, is zero.
7. In the problem state, the result of
ANDing the authorization key mask
(AKM) with the PSW-key mask in
control register 3 during PROGRAM CALL produces a result of zero.
The operation is suppressed.
The instruction-length code is 1, 2, or
3.
The privileged-operation exception is indicated by a program-interruption code
of 0002 hex (or 0082 hex if a concurrent PER event is indicated). Protection Exception
A protection exception is recognized
when any of the following is true:
1. Key-Controlled Protection: The CPU attempts to access a storage
location that is protected against the type of reference, and the
access key does not match the stor­
age key.
2. low-Address Protection: The CPU attempts a store that is subject to
low-address protection, the effec­
tive address is in the range 0-511, and the low-address protection
control, bit 3 of control register 0, is one.
3. Segment Protection: The CPU attempts to store, with DAT on, into a segment which has the
segment-protection bit set to one. Chapter 6. Interruptions 6-23

The operation is suppressed when the
location of the instruction is protected
against fetching. Similarly, the opera­
tion is suppressed when the location of
the target instruction of EXECUTE is
protected against fetching.
Except for some specific instructions
whose execution is suppressed, the oper­
ation is terminated when a protection
exception is encountered during a refer­ ence to an operand location. See the
figure "Summary of Action for Protection
and Addressing Exceptions," which is included in the section "Addressing
Exception" in this chapter.
For termination, changes may occur only
to result fields. In this context, the
term "result field" includes condition
code, registers, and storage locations,
if any, which are due to be changed by
the instruction. However, no change is made to a storage location when a refer­ ence to that location causes a protection exception. Therefore, if an
instruction is due to change only the
contents of a field in storage, and every byte of that field would cause a protection exception, the operation is
suppressed. When termination occurs on
fetching, the protected information is
not loaded into an addressable register
nor moved to another storage location.
When the exception occurs during fetch­
ing of an instruction, it is unpredict­ able whether the ILC is 1, 2, or 3.
When the exception occurs during the
fetching of the target of EXECUTE, the
IlC is 2.
For a protected operand location, the
instruction-length code (ILC) is 1, 2,
or 3, indicating the length of the
instruction that caused the reference.
However, on some models without the translation facility, an IlC of 0 occurs when a protection exception is recog­ ni=ed for a store-type reference. The protection exception is indicated by
a program-interruption code of 0004 hex
(or 0084 hex if a concurrent PER event is indicated).
Secondary-Authority Exception
A secondary-authority exception is recognized during ASH authorization in SET SECONDARY ASH with space switching (SSAR-ss) when either:
1. The authority-table entry indicated
by the authorization index in
control register 4 is beyond the length of the authority table
designated by the ASN-second-table entry.
6-24 System/370 Principles of Operation 2. The secondary-authority bit indi­
cated by the authorization index is
zero.
The ASH being translated is stored at
real locations 146-147, and real
locations 144-145 are set to zeros.
The operation is nullified.
The instruction-length code is 2.
The secondary-authority exception is
indicated by a program-interruption code
of 0025 hex (or OOA5 hex if a concurrent
PER event is indicated).
Segment-Translation Exception
A segment-translation
recognized when either:
exception is
1. The segment-table entry indicated
by the segment-index portion of a
virtual address is outside the
segment table.
2. The segment-invalid bit is one.
The exception is recognized as part of the execution of the instruction that
needs the segment-table entry in the
translation of either the instruction or operand address, except for the operand address in LOAD REAL ADDRESS and TEST PROTECTION, in which case the condition is indicated by the setting of the condition code. The segment-index and page-index portion
of the virtual address causing the
exception is stored at real locations 145-147. When DAS is installed, bit 0 of real location 144 is set to zero if the virtual address was relative to the
primary address space, or it is set to one if the virtual address was relative to the secondary address space. When DAS is not installed, bi t 0 of real location 144 is set to zero. Bits 1-7
of real location 144 are set to zeros.
When 2K-byte pages are used, the right­ most 11 bits of the address stored are unpredictable; when 4K-byte pages are used, the rightmost 12 bits of the
address stored are unpredictable.
The unit of operation is nullified.
When the exception occurs during fetch­
ing of an instruction, it is unpredict­ able whether the ILC is 1, 2, or 3.
When the exception occurs during the
fetching of the target of EXECUTE, the
ILC is 2.
When the exception occurs during a reference to an operand location, the
instruction-length code (IlC) is 1, 2,
or 3 and indicates the length of the
instruction causing the exception.