GA22-7000-10 IBM System/370 Principles of Operation Sept 1987 Page 10-15 (274 of 558)

When (1) PASH translation is called for
and completed and (2) either the current
space-switch-event-control bit, bit 31
of control register 1 is one or the space-switch-event-control bit in the ASH-second-table entry ;s one, condition
code 3 is set, and the control registers are not changed. When SASH translation is called for and
the translation cannot be completed because bit 0 is one in either the ASH first-table or ASH-second-table entries, or because SASH authorization is called
for and the SASH is not authorized,
condition code 2 is set, and the control
registers are not changed.
Special Conditions
The instruction can be executed only when the ASH-translation control, bit 12
of control register 14, is one. If the
ASH-translation-control bit is zero, a
special-operation exception is recog nlzed. The first operand must be designated on
a doubleword boundary; otherwise, a
specification exception is recognized. The operation is suppressed on all
addressing and protection exceptions.
The figures "Summary of Actions: LOAD ADDRESS SPACE PARAMETERS" and "Priority
of Execution: LOAD ADDRESS SPACE PARAM ETERS" summarize the functions of the
instruction and the priority of recogni
tion of exceptions and condition codes.
Resulting Condition Code: o
1
2 3 Translation and authorization
complete; parameters loaded
Primary ASH not available;
parameters not loaded Secondary ASH not available or
not authorized; parameters not
loaded Space-switch event specified;
parameters not loaded
Program Exceptions:
Access (fetch, operand 1)
Addressing (ASH-first-table entry,
ASH-second-table entry,
authority-table entry) ASH-translation specification
Operation (if the dual-address-
space facility is not
installed)
Privileged operation
Special operation
Specification Chapter 10. Control Instructions 10-15

1.-6. Exceptions with the same priority as the priority of program
interruption conditions for the general case.
7.A Access exceptions for second and third instruction halfwords.
7.B.1 Operation exception if the dual-address-space facility is not
installed.
7.B.2 Privileged-operation exception.
7.B.3 Special-operation exception due to the ASH-translation control,
bit 12 of control register 14, being zero.
8. Specification exception.
9. Access exceptions for the first operand. 10. Execution of PASH translation (when performed). 10.1 Addressing exception for access to ASH-first-table entry. 10.2 Condition code 1 due to I bit (bit 0) in ASH-first-table entry
being one. 10.3 ASH-translation-specification exception due to invalid ones (bits
1-7, 28-31) in ASH-first-table entry. 10.4 Addressing exception for access to ASH-second-table entry. 10.5 Condition code 1 due to I bit (bit 0) in ASH-second-table entry
being one. 10.6 ASH-translation-specification exception due to invalid ones (bits
1-7, 30, 31, 60-63, 97-103) in ASH-second-table entry. 10.7 Condition code 3 due to either the old or new space-switch-event
control bit being one.
11. Execution of SASH translation (when performed).
11.1 Addressing exception for access to ASH-first-table entry.
11.2 Condition code 2 due to I bit (bit 0) in ASH-first-table entry
being one.
11.3 ASH-translation-specification exception due to invalid ones (bits
1-7, 28-31) in ASH-first-table entry.
11.4 Addressing exception for access to ASH-second-table entry.
11.5 Condition code 2 due to I bit (bit 0) in ASH-second-table entry
being one.
11.6 ASH-translation-specification exception due to invalid ones (bits
1-7, 30, 31, 60-63, 97-103) in ASH-second-table entry.
12. Execution of secondary authorization (when performed).
12.1 Condition code 2 due to authority-table entry being outside table.
12.2 Addressing exception for access to authority-table entry.
12.3 Condition code 2 due to S bit in authority-table entry being zero.
Priority of Execution: LOAD ADDRESS SPACE PARAMETERS 10-16 System/370 Principles of Operation

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Extracted Text (may have errors)

When (1) PASH translation is called for
and completed and (2) either the current
space-switch-event-control bit, bit 31
of control register 1 is one or the space-switch-event-control bit in the ASH-second-table entry ;s one, condition
code 3 is set, and the control registers are not changed. When SASH translation is called for and
the translation cannot be completed because bit 0 is one in either the ASH first-table or ASH-second-table entries, or because SASH authorization is called
for and the SASH is not authorized,
condition code 2 is set, and the control
registers are not changed.
Special Conditions
The instruction can be executed only when the ASH-translation control, bit 12
of control register 14, is one. If the
ASH-translation-control bit is zero, a
special-operation exception is recog nlzed. The first operand must be designated on
a doubleword boundary; otherwise, a
specification exception is recognized. The operation is suppressed on all
addressing and protection exceptions.
The figures "Summary of Actions: LOAD ADDRESS SPACE PARAMETERS" and "Priority
of Execution: LOAD ADDRESS SPACE PARAM ETERS" summarize the functions of the
instruction and the priority of recogni
tion of exceptions and condition codes.
Resulting Condition Code: o
1
2 3 Translation and authorization
complete; parameters loaded
Primary ASH not available;
parameters not loaded Secondary ASH not available or
not authorized; parameters not
loaded Space-switch event specified;
parameters not loaded
Program Exceptions:
Access (fetch, operand 1)
Addressing (ASH-first-table entry,
ASH-second-table entry,
authority-table entry) ASH-translation specification
Operation (if the dual-address-
space facility is not
installed)
Privileged operation
Special operation
Specification Chapter 10. Control Instructions 10-15

1.-6. Exceptions with the same priority as the priority of program
interruption conditions for the general case.
7.A Access exceptions for second and third instruction halfwords.
7.B.1 Operation exception if the dual-address-space facility is not
installed.
7.B.2 Privileged-operation exception.
7.B.3 Special-operation exception due to the ASH-translation control,
bit 12 of control register 14, being zero.
8. Specification exception.
9. Access exceptions for the first operand. 10. Execution of PASH translation (when performed). 10.1 Addressing exception for access to ASH-first-table entry. 10.2 Condition code 1 due to I bit (bit 0) in ASH-first-table entry
being one. 10.3 ASH-translation-specification exception due to invalid ones (bits
1-7, 28-31) in ASH-first-table entry. 10.4 Addressing exception for access to ASH-second-table entry. 10.5 Condition code 1 due to I bit (bit 0) in ASH-second-table entry
being one. 10.6 ASH-translation-specification exception due to invalid ones (bits
1-7, 30, 31, 60-63, 97-103) in ASH-second-table entry. 10.7 Condition code 3 due to either the old or new space-switch-event
control bit being one.
11. Execution of SASH translation (when performed).
11.1 Addressing exception for access to ASH-first-table entry.
11.2 Condition code 2 due to I bit (bit 0) in ASH-first-table entry
being one.
11.3 ASH-translation-specification exception due to invalid ones (bits
1-7, 28-31) in ASH-first-table entry.
11.4 Addressing exception for access to ASH-second-table entry.
11.5 Condition code 2 due to I bit (bit 0) in ASH-second-table entry
being one.
11.6 ASH-translation-specification exception due to invalid ones (bits
1-7, 30, 31, 60-63, 97-103) in ASH-second-table entry.
12. Execution of secondary authorization (when performed).
12.1 Condition code 2 due to authority-table entry being outside table.
12.2 Addressing exception for access to authority-table entry.
12.3 Condition code 2 due to S bit in authority-table entry being zero.
Priority of Execution: LOAD ADDRESS SPACE PARAMETERS 10-16 System/370 Principles of Operation

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control registers 1, 5, and 7. When the
steps are not successful, no control
registers are changed, and the reason is
indicated in the condition code.
The doubleword first operand contains a
PSW-key mask (PKM), a secondary ASH (SASH), an authorization index (AX), and
a primary ASH (PASH). The primary ASH is translated by means of the ASH translation tables to obtain a PSTD,
LTD, and, optionally, an AX. The
secondary ASH is translated by means of
the ASH-translation tables to obtain an
SSTD, and, optionally, an authority
check is made to ensure that the new AX
is authorized to establish the new SASH. The doubleword at the first-operand
location has the following format:
PKM-d SASH-d AX-d PASN-d
o 16 32 48 63 The "d" stands for designated doubleword
and is used to distinguish these fields
from other fields with similar names
which are referred to in the definition.
The current contents of the correspond
ing fields in the control registers are
referred to as PKM-old, SASH-old, etc.
The updated contents of the control
registers are referred to as PKM-new,
SASH-new, etc.
The second-operand address is not used
to address data; instead, the rightmost
three bits are used to control portions
of the operation. The remainder of the
second-operand address is ignored. Bits
29-31 of the second-operand address are
used as follows:
Function Specified
in Second Operand
Bit When Bit I s Zero When Bit Is One
29 ASH translation ASH translation
performed only performed.*
when new ASH and
old ASH are dif-
ferent. 30 Use AX associ-Use AX from
ated with PASH. first operand. 31 SASH authoriza- SASH authoriza-
tion performed.* tion not per-
formed. * SASH translation and SASH authori-
zation are performed only when SASH-d is not equal to PASH-d.
When SASN-d is equal to PASH-d, the SSTD is loaded from the PSTD,
and no authorization is performed.
The operation
PARAMETERS is
of LOAD ADDRESS
depicted in the SPACE figure
"Execution of LOAD ADDRESS SPACE PARAME TERS." PASH Translation
In the PASH translation process, the
PASH-d is translated by means of the ASH first table and the ASH second table.
The STD and LTD fields and, optionally,
the AX field, obtained from the ASH second-table entry are subsequently used
to update the corresponding control
registers.
When bit 29 of the second-operand
address is one, PASH translation is
always performed. When bit 29 is zero, PASH translation is performed only when
PASH-d is not equal to PASH-old. When
bit 29 is zero and PASH-d is equal to
PASH-old, the PSTD-old and LTD-old are
left unchanged in the control registers
and become the PSTD-new and LTD-new,
respectively. In this case, if bit 30 i s zero, then the AX-o 1 dis left
unchanged in the control register and
becomes the AX-new.
The PASN translation follows the normal
rules for ASH translation, except that
the invalid bits, bit 0 in the ASH first-table entry and bit 0 in the ASH second-table entry, when ones, do not
result in an ASH-translation exception,
and the space-switch-event-control bit
in the ASH-second-table entry, when one,
does not result in a space-switch event.
When either of the invalid bits is one,
condition code 1 is set. When the ASH second-table entry is valid and either
the current space-switch-event-control
bit in control register 1 is one or the
space-switch-event-control bit in the
ASH-second-table entry is one, condition
code 3 is set. When condition code 1 or
3 is set, the control registers remain
unchanged.
The contents of the AX, STD, and LTD
fields in the ASH-second-table entry
which is accessed as a result of the PASH translation are referred to as
AX-p, STD-p, and LTD-p, respectively.
SASH Translation
In the SASH-translation process, the SASH-d is translated by means of the ASH first table and the ASH second table.
The STD field obtained from the ASH
second-table entry is subsequently used
to update the secondary-segment-table
designation (S5TD) in control register
7. The ATO and ATL fields obtained are
used in the SASH authorization, if it
occurs. Chapter 10. Control Instructions 10-13

SASH translation is performed only when SASH-d is not equal to PASH-d. When
SASH-d is equal to PASN-d, the SSTD-new is set to the same value as PSTD-new. When SASH-d is equal to SASH-old, bit 29
(force ASH translation) is zero, and bit 31 (skip SASH authorization) is one,
then SASH translation is not performed,
and SSTD-old becomes SSTD-new.
The SASH translation follows the normal
rules for ASH translation, except that
the invalid bits, bit 0 in the ASH first-table entry and bit 0 in the ASH second-table entry, when ones, do not
result in an ASH-translation exception.
When either or both of the invalid bits
are ones, condition code 2 is set, and
the control registers remain unchanged.
The contents of the STD, ATO, and ATl
fields in the ASH-second-table entry
which is accessed as a result of the SASH translation are referred to as
STD-s, ATO-s, and ATl-s, respectively. SASH Authorization SASH authorization is performed when bit
31 of the second-operand address is zero
and SASH-d is not equal to PASH-d. When SASH-d is equal to PASH-d or when bit 31 of the second-operand address is one, SASH authorization is not performed. SASH authorization is performed by using ATO-s, ATl-s, and the intended value for
AX-new. When bit 30 of the second
operand address is zero and PASH trans
lation was performed, the intended value
for AX-new is AX-p. When bit 30 of that
address is zero and PASH translation was
not performed, the AX is not changed,
and AX-new is the same as AX-old. When
bit 30 of that address is one, the
intended value for AX-new is AX-d. SASH authorization follows the rules for
secondary authorization as described in the section "ASH-Authorization Process" in Chapter 3, "Storage." If the SASH is
not authorized (that is, the authority
table length is exceeded, or the
selected bit is zero), condition code 2
is set, and none of the control regis
ters are updated.
Control-Register loading
When the PASH-translation, SASH translation, and SASH-authorization
functions, if called for in the opera
tion, are performed without encountering
any exceptions, the operation is
completed by replacing the contents of
control registers 1, 3, 4, 5, and 7 with
the new values, and condition code 0 is
set. The control registers are loaded
as follows: 10-14 System/370 Principles of Operation The PSW-key-mask and SASH fields in
control register 3 are replaced by the
PKM-d and SASH-d fields from the first
operand location.
The PASH, bits 16-31 of control register
4, is replaced by the PASH-d field from
the first-operand location.
The authorization index, bits 0-15 replaced
of
as control register 4, is follows: • When bit 30 of the second-operand
address is one, from AX-d. • When bit 30 of the second-operand
address is zero and PASH trans
lation is performed, from AX-p. • When bit 30 of the second-operand
address is zero and PASH trans
lation is not performed, the
authorization index is not changed.
The primary-segment-table designation in
control register 1 and the linkage-table
designation in control register 5 are
replaced as follows: • When PASH translation is performed,
the primary-segment-table designa
tion in control register 1 and the
linkage-table designation in
control register 5 are replaced
from the STD-p and lTD-p fields,
respectively, which are obtained
during PASH translation. • When PASH translation is not
performed, the primary-segment
table-designation and linkage
table-designation fields remain
unchanged.
The contents of the secondary-segment
table designation in control register 7 are replaced as follows: • When SASH-d equals PASH-d, by the
new contents of control register 1,
the primary-segment-table desig
nation. • When SASH translation is performed,
by the contents of the STD-s.
When SASH-d does not equal PASH-d and SASH translation is not performed, the
secondary-segment-table designation re
mains unchanged.
other Condition-Code Settings
When PASH translation is called for and
cannot be completed because bit 0 is one
in either the ASH-first-table or the
ASH-second-table entries, condition code
1 is set, and the control registers are
not changed.

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Second- Operand- Address
PASN-d Bits* PASN Result Field Equals Translation
PASN-old 29 30 Performed PSTD-new AX-new LTD-new PKM-new SASN-new Yes 0 0 No PSTD-old AX-old LTD-old PKM-d SASN-d Yes 0 1 No PSTD-old AX-d LTD-old PKM-d SASN-d Yes 1 0 Yes STD-p AX-p LTD-p PKM-d SASN-d Yes 1 1 Yes STD-p AX-d LTD-p PKM-d SASN-d
No - 0 Yes STD-p AX-p LTD-p PKM-d SASN-d
No -1 Yes STD-p AX-d LTD-p PKM-d SASN-d
Summary of Actions: LOAD ADDRESS SPACE PARAMETERS (Part 1 of 2)
Second-Ope rand- SASN-d SASN-d Address Bits* SASN SASN Equals Equals Translation Authorization Result Field PASN-d SASN-old 29 31 Performed PerformedU SSTD-new Yes - - - No No PSTD-new No Yes 0 1 No No SSTD-old
No Yes 1 1 Yes No STD-s
No Yes - 0 Yes Yes STD-s No No -1 Yes No STD-s
No No - 0 Yes Yes STD-s
Explanation:
- Action in this case is the same regardless of the outcome of this
comparison or of the setting of this bit. * Second-operand-address bits:
29 Force ASN translation. 30 Use AX from first operand.
31 Skip secondary authority test. U SASN authorization is performed using ATO-s, ATl-s, and AX-new.
Summary of Actions: LOAD ADDRESS SPACE PARAMETERS (Part 2 of 2)
PASN-new
PASN-d
PASN-d PASN-d PASN-d PASN-d PASN-d
Chapter 10. Control Instructions 10-17

Programming Notes
1. Bits 29 and 31 in the second
operand address are intended prima rily to provide improved
performance for those cases where
the associated action is unneces
sary.
When bit 29 is set to zero, the
action of the instruction is based
on the assumption that the current
values for PSTD-old, LTD-old, and AX-old are consistent with PASH-old and that SSTD-old is consistent
with SASH-old. When this is not
the case, bit 29 should be set to
one.
Bit 31, when one, eliminates the SASH-authorization test. The
program may be able to determine in
certain cases that the SASH is authorized, either because of prior
use or because the AX being loaded
is authorized to access all address
spaces.
2. The SASH-translation and SASH authorization steps are not
performed when SASH-d is equal to PASH-d. This is consistent with
the action in SET SECONDARY ASN to
current primary (SSAR-cp), which does not perform the translation or ASH authorization.
3. See the figure "Summary of Abbrevi
ations for LOAD ADDRESS SPACE PARAMETERS" for a listing of abbre viations used in this instruction
description. 10-18 System/370 Principles of Operation
Abbreviation for Control- Register Previous Subsequent Humber.Bit Contents Contents 1.0-31 PSTD-old PSTD-new 3.0-15 PKM-old PKM-new
3.16-31 SASH-old SASH-new 4.0-15 AX-old AX-new
4.16-31 PASH-old PASN-new 5.0-31 LTD-old LTD-new 7.0-31 SSTD-old SSTD-new First-Operand
Bit Positions Abbreviation 0-15 PKM-d
16-31 SASN-d 32-47 AX-d 48-63 PASN-d Abbreviation Used for
the Field When Accessed
as Part of
Field in ASN- Second-Table PASH SASN Entry Translation Translation
8-29 -ATO-s
32-47 AX-p -
48-59 -ATL-s
64-95 STD-p STD-s
96-127 LTD-p
_1 Ex~lanation: - The field i s not used in this
case.
1
Although the field is not used,
bits 97-103 are tested for zeros. Summary of Abbreviations for LOAD ADDRESS SPACE PARAMETERS

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