Table- Instruction
Exception Entry Fetch
l
Fetch Operand Reference
Addressing Suppress exception Suppress Suppress for IPTE, LASP, LPSW, SCKC, SPT, SPX, SSM, STHSM, STOSM, TPROT, and DAS tracing.
2
Terminate for all others.3
Protection
exception
for key­
controlled
protection Suppress Suppress for IPTE, LASP, LPSW, SCKC, SPT, SPX, SSM, STHSM, and STOSM. Terminate for all others.
3 Protection exception
for seg­
ment
protection Suppress for STHSM, STOSM, and DAS trac;ng.
2
Terminate for all others.3
Protection
exception
for low­
address
protection Suppress for IPTE, STNSM, STOSM, and DAS tracing.
2
Terminate for all others.
3
Explanation:
-- Hot applicable.
1
2
3
Table entries include segment table, page table, linkage
table, entry table, ASH first table, ASH second table,
authority table, trace-table designation, trace-table­
entry header, and CPU-identity byte.
The following instructions may cause an entry to be made
in the trace table when DAS tracing is active: PC, PT, and SSAR. The stores into the current-entry-control
word and the trace entry are subject to addressing, seg­
ment-protection, and low-address-protection exceptions.
The operation is suppressed for these exceptions.
For termination, changes may occur only to result
fields. In this context, "result field" includes con­
dition code, registers, and storage locations, if any,
which are designated to be changed by the instruction.
However, no change is made to a storage location or a storage key when the reference causes an access excep­
tion. Therefore, if an instruction is due to change
only the contents of a field in main storage, and every
byte of that field would cause an access exception,
the result is the same as if the operation had been
suppressed. Summary of Action for Addressing and Protection Exceptions Chapter 6. Interruptions 6-17

AFX-Translation Exception An AFX-translation exception is recog­ nized when, during ASH translation in PROGRAM CAll with space switching (PC-ss), PROGRAM TRANSFER with space switching (PT-ss), or SET SECONDARY ASN with space switching (SSAR-ss), bit 0 of the ASN-first-table entry used is not
zero.
The ASN being translated is stored at
real locations 146-147, and real locations 144-145 are set to zeros. The operation is nullified. The instruction-length code is 2.
The AFX-translation exception is indi­
cated by a program-interruption code of 0020 hex (or OOAO hex if a concurrent PER event is indicated).
ASN-Translation-Specification Exception
An ASN-translation-specification excep­
tion is recognized during ASN trans­
lation in LOAD ADDRESS SPACE PARAMETERS, PROGRAM CALL with space switching (PC-55), PROGRAM TRANSFER with space
switching (PT-ss), or SET SECONDARY ASN with space switching (SSAR-ss) when either: 1. Bit positions 1-7 and 28-31 of a
valid ASN-first-table entry do not
contain zeros.
2. Bit positions 1-7, 30, 31, 60-63, and 97-103 of a valid ASN-second­ table entry do not contain zeros.
The operation is suppressed.
The instruction-length code is 2 or 3.
The ASH-translation-specification excep­
tion is indicated by a program­
interruption code of 0017 hex (or 0097 hex if a concurrent PER event is indi­
cated).
ASX-Translation Exception
An ASX-translation exception is recog­
nized when, during ASN translation in PROGRAM CAll with space switching (PC-ss), PROGRAM TRANSFER with space
switching (PT-ss), or SET SECONDARY ASN with space switching (SSAR-ss), bit 0 of the ASH-second-table entry used is not
zero.
6-18 System/370 Principles of Operation The ASH being translated is stored at real locations 146-147, and real locations 144-145 are set to zeros.
The operation is nullified.
The instruction-length code is 2.
The ASX-translation exception is indi­
cated by a program-interruption code of 0021 hex (or 00A1 hex if a concurrent PER event is indicated).
Data Exception
A data exception is recognized when any
of the following is true:
1. The sign or digit codes of operands
1n the decimal instructions
(described in Chapter 8, "Decimal
Instructions") or in COHVERT TO BINARY are invalid.
2. The operand fields in ADD DECIMAL, COMPARE DECIMAL, DIVIDE DECIMAL, MULTIPLY DECIMAL, and SUBTRACT DECIMAL overlap in a way other than
with coincident rightmost bytes; or
operand fields in ZERO AND ADD
overlap, and the rightmost byte of
the second operand is to the right
of the rightmost byte of the first
operand.
3. The multiplicand in MULTIPLY DECI­
MAL has an insufficient number of
leftmost zeros. The action taken for a data exception
depends on whether a sign code is inval­
id. The operation is suppressed when a
sign code is invalid, regardless of
whether any other condition causing the
exception exists; when no sign code is
invalid, the operation is terminated.
For all instructions other than EDIT and
EDIT AND MARK, when the operation is
terminated, the contents of the sign
position in the rightmost byte of the
result field either remain unchanged or
are set to the preferred sign code; the
contents of the remainder of the result
field are unpredictable.
In the case of EDIT and EDIT AND MARK,
an invalid sign code cannot occur; the
operation is terminated on a data excep­
tion for an invalid digit code.
The instruction-length code is 2 or 3.
The data exception is indicated by a
program-interruption code of 0007 hex
(or 0087 hex if a concurrent PER event is indicated).