entry is described as attached, the term
"to a CPU" is implied.
The usable state of a TLB entry denotes
that the CPU can attempt to use the TLB
entry for implicit address translation.
Also, the usable state of a TLB
segment-table entry is a factor in
determining whether a page-table entry
is attached.
A segment-table entry or a page-table
entry may be placed in the TLB only when
the entry is attached and valid and
would not cause a translation­
specification exception if used for
translation. Except for these
restrictions, the entry may be placed in the TLB at any time. A segment-table entry is attached when
all of the following conditions are met:
1. The current PSW specifies DAT on.
2. The current PSW contains no errors
which would cause an early excep­ tion to be recognized. Those
machines without DAS installed do
not necessarily comply with this condition.
3. The current translation format,
bits 8-12 in control register 0, is
valid.
4. The entry meets the requirements in
a or b below.
a. The entry is within the segment
table designated by the prlmary
segment-table designation in
control register 1.
b. The entry is within the segment
table designated by the second­
ary segment-table designation
in control register 7 and
either of the following
requirements is met:
•
•
The CPU is in the
secondary-space mode.
The secondary-space con­
trol, bi t 5 of control
register 0, is one.
5. The entry can be selected by the
segment-index portion of a virtual
address.
A page-table entry is attached when it
is within the page table designated by
either a usable TLB segment-table entry
or by an attached and valid segment­
table entry which would not cause a
translation-specification exception if
used for translation.
A TLB segment-table entry is in the
usable state when all of the following
conditions are met:
1 .
2.
3.
4.
The current PSW specifies DAT on.
The current PSW contains no errors
which would cause an early excep­
tion to be recognized. Those
machines without DAS installed do
not necessarily comply with this
condition.
The translation-format field in the
TLB segment-table entry is the same
as the current translation format.
The TLB segment-table entry meets
at least one of the following re­
quirements:
• The common-segment bit is one
in the TLB entry.
• The segment-table-origin field in the TLB entry is the same as
the current PSTO.
• The segment-table-origin field
in the TlB entry is the same as
the current SSTO, and either PSW bit 16 is one or bit 5 of
control register 0 is one.
A TLB segment-table entry may be used
for implicit address translation only
when the entry is in the usable state,
the segment index of the entry matches
the segment index of the virtual address
to be translated, and either the
common-segment bit is one in the TLB
entry or the segment-table-origin field
in the TLB entry matches the segment­
table origin used to select it.
A TlB page-table entry
state when all of the
tions are met:
is in the usable
following condi-
1 . The TLB page-table entry is selected by a usable TlB segment­
table entry or by an attached and
valid segment-table entry which
would not cause a translation­
specification exception if used for
translation .
2. The page-table-origin field in the
TlB page-table entry matches the
page-table-origin field in the
segment-table entry which selects
it.
3. The page-index field in the TlB
page-table entry is within the
range permitted by the page-table­
length field in the segment-table
entry which selects it.
4. The translation-format field in the
TlB page-table entry is the same as
the current translation format.
A TlB page-table entry may be used for
implicit address translation only when
the TlB entry is in the usable state as
selected by the segment-table entry
being used and only when the page index Chapter 3. Storage 3-33

of the TLB page-table entry matches the
page index of the virtual address being
translated.
The operand address of LOAD REAL ADDRESS
is translated without the use of the TLB
contents. Translation in this case is performed by the use of the designated
tables in real storage.
Selected page-table entries are cleared
from the TLB by means of the INVALIDATE
PAGE TABLE ENTRY instruction. All
information in the TLB is necessarily
cleared only by execution of PURGE SET PREFIX, or CPU reset.
Programming Notes
1. Although a table entry may be
copied into the TLB only when the
table entry is both valid and
attached, the copy may remain in
the TLB even when the table entry
itself is no longer valid or
attached.
2. No entries can be copied into the
TLB when DAT is off because the
table entries at this time are not
attached. In particular, trans­
lation of the operand address of LOAD REAL ADDRESS, with OAT does not cause entries to be placed
in the TLB.
3-34 System/370 Principles of Operation
Conversely, when DAT is on, infor­
mation may be copied into the TLB
from all translation-table entries
that could be used for address
translation, given the current
translation parameters, the setting
of the address-space-control and the setting of the secondary­
space-control bit. The loading of
the TLB does not depend on whether
the entry is used for translation
as part of the execution of the
current instruction, and such load­
ing can occur when the wait state
is specified.
3. More than one copy of a table entry
may exist in the TLB. For example,
some implementations may cause a
copy of a valid table entry to be
placed in the TLB for each
segment-table origin by which the
entry becomes attached.
4. The segment size controls how many
segment-table entries can be
referred to for translation. Both
the page size and segment size
control the selection of page-table
entries and hence may affect wheth­
er or not an entry is attached.
5. The states and use of the OAT entries in both real storage and in
the TLB are summarized in the
figure "Summary of OAT Entries."