Explanation (Continued): Preserve The contents of the entire checking block having invalid CBC are left unchanged.
Validate The entire key is set to the new value with valid CBC. CPF Invalid CBC in the storage key for a CPU prefetch which
is unused, or for instructions which do not examine the
reference and change bits, may result in any of the fol­
lowing situations: • The operation is completed; no machine-check condi­
tion is reported. • The operation is completed; system recovery, with
storage-key error uncorrected, is reported. • Instruction-processing damage, with or without backup
and with storage-key error uncorrected, is reported. IPF Invalid CBC in the storage key for a channel-program pre­
fetch which is unused may result in any of the following: • The I/O operation is completed; no machine-check con­
dition is reported. • The I/O operation is completed; system recovery, with
storage-key error uncorrected, is reported. • An I/O-error condition is reported; no machine-check
condition is reported. • An I/O-error condition is reported; system recovery,
with storage-key error uncorrected, is reported. • The I/O operation is completed, or an I/O-error condi­
tion is reported; external damage, with or without
storage-key error uncorrected, is reported. • The I/O operation is completed, or an I/O-error condi­
tion is reported; external damage, with a valid
external-damage code, with external secondary report,
and with storage-key error uncorrected, is reported. MC Same as PO for CPU references, but a channel-program ref­
erence may result in the following combinations of 1/0- error conditions and machine-check conditions: • An I/O-error condition is reported; no machine-check
condition is reported. • An I/O-error condition is reported; system recovery,
with or without storage-key error uncorrected, is re­
ported. • The I/O operation is completed, or an I/O-error condi­
tion is reported; external damage, with or without
storage-key error uncorrected, is reported. • An I/O-error condition is reported; external damage,
with a valid external-damage code, with external
secondary report, and with storage-key error uncor­
rected, is reported. PO Instruction-processing damage, with or without backup and
with or without a storage-key error uncorrected, is re­
ported.
Note: When storage-key error uncorrected is reported, a failing­
storage address mayor may not also be reported.
Invalid CBC in Storage Keys (Part 2 of 2)
INVALID CSC IN REGISTERS
When invalid CBC is detected in a CPU register, a machine-check condition may
be recognized. CPU registers include
the general, floating-point, and control
registers, the current PSW, the prefix
register, the TOO clock, the CPU timer,
and the clock comparator.
When a machine-check interruption
occurs, whether or not it is due to
invalid CSC in a CPU register, the
following actions affecting the CPU registers, other than the prefix regis­
ter and the TOO-clock, are taken as part
of the interruption. Chapter 11. Machine-Check Handling 11-9

1. The contents of the registers are
saved in assigned storage loca­
tions. Any register which is in
error is identified by a corre­
sponding validity bit of zero in
the machine-cheek-interruption
code. Malfunctions detected during
register saving do not result in
additional machine-cheek-interrup­
tion conditions; instead, the
correctness of all the information
stored is indicated by the appro­
priate setting of the validity
bits.
2. On some models, registers with
invalid CBC are then validated,
their actual contents being unpre­
dictable. On other models,
programmed validation is required.
The prefix register and the TOD clock
are not stored during a machine-check
interruption, have no corresponding
validity bit, and are not validated. On those models in which registers are not automatically validated as part of
the machine-check interruption, a regis­
ter with invalid CBC will not cause a machine-cheek-interruption condition
unless the contents of the register are
actually used. In these models, each
register may consist of one or more
checking blocks, but multiple registers are not included in a single checking
block. When only a portion of a regis­
ter is accessed, invalid CBC in the
unused portion of the same register may
cause a machine-cheek-interruption
condition. For example, invalid CBC in
the right half of a floating-point
register may cause a machine-check­
interruption condition if a LOAD (LE)
operation attempts to replace the left
half, or short form, of the register.
Invalid CBC associated with the check­
stop-control bit (control register 14, bit 0) and with the asynchronous fixed­
logout-control bit (control register 14,
bit 9) will cause the CPU either to
enter the check-stop state immediately
or to assume that bits 0 and 9 have
their initialized values of one and zero, respectively.
Invalid CBC associated with the prefix
register cannot safely be reported by
the machine-check interruption, since
the interruption itself requires that
the prefix value be applied to convert
real addresses to the corresponding
absolute addresses. Invalid CBC in the
prefix register causes the CPU to enter
the check-stop state immediately when
the check-stop-control bit (control
register 14, bit 0) is one. When the
check-stop-control bit is zero, the
machine is permitted to ignore even the
most severe errors; thus, invalid CBC in
the prefix register may be ignored or
may cause the CPU to enter the check­
stop state.
11-10 System/370 Principles of Operation On those models which do not validate
registers during a machine-check inter­
ruption, the following instructions will
cause validation of a register, provided
the information in the register is not
used before the register is validated.
Other instructions, although they
replace the entire contents of a regis­
ter, do not necessarily cause
validation.
General registers are validated by BRANCH AND LINK (BAl, BAlR), LOAD (LR),
and LOAD ADDRESS. LOAD (L) and LOAD MULTIPLE validate if the operand is on a
word boundary, and LOAD HALFWORD vali­
dates if the operand is on a halfword
boundary.
Floating-point registers are validated
by LOAD (LDR) and, if the operand is on a doubleword boundary, by LOAD (lD). Control registers may be validated
either singly or in groups by using the
instruction LOAD CONTROL. The CPU timer, clock comparator, and
prefix register are validated by SET CPU TIMER, SET CLOCK COMPARATOR, and SET PREFIX, respectively.
The TOD clock is validated by SET CLOCK if the TOD-clock control is in the
enable-set position. Programming Note
Depending on the register, and the
model, the contents of a register may be
validated by the machine-check inter­
ruption or the model may require that a
program execute a validating instruction
after the machine-check interruption has
occurred. In the case of the CPU timer,
depending orr the model, both the
machine-check interruption and validat­
ing instructions may be required to
restore the CPU timer to full working
order. CHECK-STOP STATE
In certain situations it is impossible
or undesirable to continue operation
when a machine error occurs. In these
cases, the CPU may enter the check-stop
state, which is indicated by the check­
stop indicator.
In general, the CPU may enter the
check-stop state whenever an uncorrecta­
ble error or other malfunction occurs
and the machine is unable to recognize a
specific machine-cheek-interruption
condition.