Programming Note
An example of the use of the LOAD instruction is given in Appendix A. LOAD ADDRESS
LA [RX]
'41 '
o 8 12 16 20 31
The address specified by the X 2 ' B 2 , and O 2 fields is placed in bit positions
8-31 of general register R I • Bits 0-7 of the register are set to zeros. The address computation follows the rules
for address arithmetic. No storage references place, and the address
for access exceptions.
for operands take
is not inspected Condition Code: The code remains
unchanged. Program Exceptions: None. Programming Notes 1. An example of the use of the LOAD ADDRESS instruction is given in Appendix A.
2. LOAD ADDRESS may be used to incre­ ment the rightmost 24 bits of a general register, other than regis­
ter 0, by the contents of the D2 field of the instruction. The register to be incremented should be designated by RI and by either
X
2 (with B2 set to zero) or B2 (with X
2 set to zero). LOAD AND TEST
LTR [RR] , 12 '
o 8 12 15
The second operand is placed unchanged
at the first-operand location, and the
sign and magnitude of the second
operand, treated as a 32-bit signed
binary integer, are indicated in the condition code.
Resulting Condition Code: o
1
2 3 Result zero
Result less than zero
Result greater than zero Program Exceptions: None. Programming Note
When the RI and R2 fields designate the
same register, the operation is equiv­
alent to a test without data movement. LOAD COMPLEMENT LCR R
1 ,R 2 [RR] , 13'
o 8 12 15
The two's complement of the second oper­
and is placed at the first-operand
location. The second operand and result
are treated as 32-bit signed binary
integers.
When there is an overflow, the result is
obtained by allowing any carry into the
sign-bit position and ignoring any carry
out of the sign-bit position, and condi­
tion code 3 is set. If the fixed­
point-overflow mask is one, a program
interruption for fixed-point overflow
occurs.
Resulting Condition Code: 0 Result zero; no overflow
1 Result less than zero; no over-
flow
2 Result greater than zero; no
overflow
3 Overflow Program Exceptions:
Fixed-point overflow Programming Note
The operation complements all numbers. Zero and the maximum negative number
remain unchanged. An overflow condition
occurs when the maximum negative number
is complemented. Chapter 7. General Instructions 7-21

LOAD HALFWORD LH [RX]
'48'
o 8 12 16 20 31
The second operand is considered to be
extended to a 32-bit signed binary inte­ ger and is placed at the first-operand
location. The second operand is two
bytes in length and is considered to be
a 16-bit signed binary integer. The
second operand is extended to 32 bits by
setting each of the 16 leftmost bit
positions equal to the sign bit of the
storage operand.
Condition Code:
unchanged. Program Exceptions:
The code
Access operand 2) Programming Note remains
An example of the use of the LOAD HAlF­ WORD instruction is given in Appendix A. LOAD MULTIPLE LM [RS]
'98'
o 8 12 16 20 31
The set of general registers starting
with general register R, and ending with
general register RJ is loaded from stor­ age beginning at the location designated
by the second-operand address and
continuing through as many locations as
needed.
The general registers are loaded in the
ascending order of their register starting with general register R, and continuing up to and including
general register R31 with general regis­
ter 0 following general register 15.
Condition Code:
unchanged. Program Exceptions:
The code
Access (fetch, operand 2)
remains
7-22 System/370 Principles of Operation Programming Note
All combinations of register numbers
specified by Rl and R3 are valid. When
the register numbers are only
four bytes are transmitted. When the
number specified by R3 is less than the
number specified by the register
numbers wrap around from 15 to o. LOAD NEGATIVE
LNR [RRJ
o 8 12 15
The two's complement of the absolute
value of the second operand is placed at
the first-operand location. The second
operand and result are treated as 32-bit
signed binary integers.
Resulting Condition Code:
o
1
2
3
Result zero Result less than zero Program Exceptions: None. Programming Note The operation complements positive
numbers; negative numbers remain
unchanged. The number zero remains
unchanged. LOAD POSITIVE [RR]
o 8 12 15
The absolute value of the second operand
is placed at the first-operand location.
The second operand and the result are
treated as 32-bit signed binary
integers.
When there is an overflow, the result is obtained by allowing any carry into the
sign-bit position and ignoring any carry
out of the sign-bit position, and condi­
tion code 3 is set. If the fixed­
point-overflow mask is one, a program
interruption for fixed-point overflow
occurs.