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Control General Floating-Point Registers Registers Registers R Register Field Number 1+--32 bits-~I 1+--32 bits-~I 1 ~ 64 bits ~I 0000 0 [I I 0001 1 0010 2 [I 0011 3 I [I 0100 4 I 0101 5 [I 0110 6 I 0111 7 1000 8 [I 1001 9 I [I Note: The brackets 1010 10 indicate that the two registers may be coupled as a double-register I pair, designated by 1011 11 specifying the lower- numbered register in the R field. For ex- [I ample, the general- 1100 12 register pair 14 and 15 is designated by 1110 binary in the R I field. 1101 13 [I 1110 14 I 1111 15 General, Floating-Point, and Control Registers ~ ~ Chapter 2. Organization 2-5
CHANNEL SETS The group of channels which connects to a particular CPU is called a channel set. When channel-set switching is installed in a multiprocessing config uration, the program can control which CPU is connected to a particular channel set. A CPU can be connected to no more than one channel set at a time, and a channel set can be connected to no more than one CPU at a time. When channel set switching is not installed, the channel sets, in the absence of model dependent reconfiguration controls, are permanently connected to a single CPU. CHANNELS A channel relieves the CPU of the burden of communicating directly with I/O devices and permits data processing to proceed concurrently with I/O operations. A channel is connected with main storage, with control units, and, unless it is a member of a disconnected channel set, with a cpu. A channel may be an independent unit, complete with the necessary logical and internal-storage capabilities, or it may time-share CPU facilities and be phys ically integrated with the CPU. In either case, the functions performed by a channel are identical. The maximum data-transfer rate may differ, however, depending on the implementation. There are three types of channels: byte-multiplexer, block-multiplexer, and selector channels. 2-6 System/370 Principles of Operation I/O DEVICES AND CONTROL UNITS I/O devices include such equipment as card readers and punches, magnetic-tape units, direct-access storage, displays, keyboards, printers, teleprocessing devices, communications controllers, and sensor-based equipment. Many I/O devices function with an external medium, such as punched cards or magnet ic tape. Some I/O devices handle only electrical signals, such as those found in sensor-based networks. In either case, I/O-device operation is regulated by a control unit. In all cases, the control-unit function provides the logical and buffering capabilities necessary to operate the associated I/O device. From the programming point of view, most control-unit functions merge with I/O-device functions. The control-unit function may be housed with the I/O device or in the CPU, or a sepa rate control unit may be used. OPERATOR FACILITIES The operator facilities provide the functions necessary for operator control of the machine. Associated with the operator facilities may be an operator console device, which may also be used as an I/O device for communicating with the program. The main functions provided by the oper ator facilities include resetting, clearing, initial program loading, start, stop, alter, and display.
Control General Floating-Point Registers Registers Registers R Register Field Number 1+--32 bits-~I 1+--32 bits-~I 1 ~ 64 bits ~I 0000 0 [I I 0001 1 0010 2 [I 0011 3 I [I 0100 4 I 0101 5 [I 0110 6 I 0111 7 1000 8 [I 1001 9 I [I Note: The brackets 1010 10 indicate that the two registers may be coupled as a double-register I pair, designated by 1011 11 specifying the lower- numbered register in the R field. For ex- [I ample, the general- 1100 12 register pair 14 and 15 is designated by 1110 binary in the R I field. 1101 13 [I 1110 14 I 1111 15 General, Floating-Point, and Control Registers ~ ~ Chapter 2. Organization 2-5
CHANNEL SETS The group of channels which connects to a particular CPU is called a channel set. When channel-set switching is installed in a multiprocessing config uration, the program can control which CPU is connected to a particular channel set. A CPU can be connected to no more than one channel set at a time, and a channel set can be connected to no more than one CPU at a time. When channel set switching is not installed, the channel sets, in the absence of model dependent reconfiguration controls, are permanently connected to a single CPU. CHANNELS A channel relieves the CPU of the burden of communicating directly with I/O devices and permits data processing to proceed concurrently with I/O operations. A channel is connected with main storage, with control units, and, unless it is a member of a disconnected channel set, with a cpu. A channel may be an independent unit, complete with the necessary logical and internal-storage capabilities, or it may time-share CPU facilities and be phys ically integrated with the CPU. In either case, the functions performed by a channel are identical. The maximum data-transfer rate may differ, however, depending on the implementation. There are three types of channels: byte-multiplexer, block-multiplexer, and selector channels. 2-6 System/370 Principles of Operation I/O DEVICES AND CONTROL UNITS I/O devices include such equipment as card readers and punches, magnetic-tape units, direct-access storage, displays, keyboards, printers, teleprocessing devices, communications controllers, and sensor-based equipment. Many I/O devices function with an external medium, such as punched cards or magnet ic tape. Some I/O devices handle only electrical signals, such as those found in sensor-based networks. In either case, I/O-device operation is regulated by a control unit. In all cases, the control-unit function provides the logical and buffering capabilities necessary to operate the associated I/O device. From the programming point of view, most control-unit functions merge with I/O-device functions. The control-unit function may be housed with the I/O device or in the CPU, or a sepa rate control unit may be used. OPERATOR FACILITIES The operator facilities provide the functions necessary for operator control of the machine. Associated with the operator facilities may be an operator console device, which may also be used as an I/O device for communicating with the program. The main functions provided by the oper ator facilities include resetting, clearing, initial program loading, start, stop, alter, and display.
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channel, and main-storage location can be in only one configuration at a time. MAIN STORAGE Main storage, which is directly address able, provides for high-speed processing of data by the CPUs and channels. Both data and programs must be loaded into main storage from input devices before they can be processed. The amount of main storage available on the system depends on the model, and, depending on the model, the amount in the configura tion may be under control of model dependent configuration controls. The storage is available in multiples of 2K-byte blocks. When either TEST BLOCK or the storage-key 4K-byte-block facili ty is installed, storage is available in multiples of 4K-byte blocks. At any instant in time, all CPUs and all chan nels in the configuration have access to the same blocks of storage and refer to a particular block of main-storage locations by using the same absolute address. Main storage may include a faster-access buffer storage, sometimes called a cache. Each CPU may have an associated cache. The effects, except on perform ance, of the physical construction and the use of distinct storage media are not observable by the prograM. The central processing unit (CPU) is the controlling center of the system. It contains the sequencing and processing facilities for instruction execution, interruption action, timing functions, initial program loading, and other machine-related functions. The physical implementation of the CPU may differ among models, but the logical function remains the same. The result of executing an instruction is the same for each model, providing that the program complies with the compatibility rules. The CPU, in executing instructions, can process binary integers and floating point numbers of fixed length, decimal integers of variable length, and logical information of either fixed or variable length. Processing may be in parallel or in series; the width of the process ing elements, the multiplicity of the shifting paths, and the degree of simul taneity in performing the different types of arithmetic differ from one CPU ~ to another without affecting the logical results. Instructions which the CPU executes fall into five classes: general, decimal, floating-point, control, and I/O instructions. The general instructions are used in performing binary integer arithmetic operations and logical, branching, and other nonarithmetic oper ations. The decimal instructions operate on data in the decimal format, and the floating-point instructions on data in the floating-point format. The privileged control instructions and the I/O instructions can be executed only when the CPU is in the supervisor state; the semiprivileged control instructions can be executed in the problem state, subject to the appropriate authorization mechanisms. To perform its functions, the CPU may use a certain amount of internal storage. Although this internal storage may use the same physical storage medium as maln storage, it is not considered part of main storage and is not address able by programs. The CPU provides registers which are available to programs but do not have addressable representations in main storage. They include the current program-status word (PSW), the general registers, the floating-point registers, the control registers, the prefix regis ter, and the registers for the clock comparator and the CPU timer. Each CPU in an installation provides access to a time-of-day (TOO) clock, which may be local to that CPU or shared with other CPUs in the installation. The instruc tion operation code determines which type of register is to be used in an operation. See the figure "General, Floating-Point, and Control Registers" later in this chapter for the format of those registers. PSW The program-status word (PSW) includes the instruction address, condition code, and other information used to control instruction sequencing and to determine the state of the CPU. The active or controlling PSW is called the current PSW. It governs the program currently being executed. The CPU has an interruption capability, which permits the CPU to switch rapidly to another program in response to excep tional conditions and external stimuli. When an interruption occurs, the CPU places the current PSW in an assigned storage location, called the old-PSW location, for the particular class of interruption. The CPU fetches a new PSW from a second assigned storage location. This new PSW determines the next program to be executed. When it has finished processing the interruption, the inter- Chapter 2. Organization 2-3
rupting program may reload the old PSW, making it again the current PSW, so that the interrupted program can continue. There are six classes of interruption: external, I/O, machine check, program, restart, and supervisor call. Each class has a distinct pair of old-PSW and new-PSW locations permanently assigned in real storage. GENERAL REGISTERS Instructions may designate information in one or more of 16 general registers. The general registers may be used as base-address registers and index regis ters in address arithmetic and as accu mulators in general arithmetic and logical operations. Each register contains 32 bits. The general registers are identified by the numbers 0-15 and are designated by a four-bit R field in an instruction. Some instructions provide for addressing multiple general registers by having several R fields. For some instructions, the use of a specific general register is implied rather than explicitly designated by an R field of the instruction. For some operations, two adjacent gener al registers are coupled, providing a 64-bit format. In these operations, the program must designate an even-numbered register, which contains the leftmost (high-order) 32 bits. The next higher numbered register contains the rightmost (low-order) 32 bits. In addition to their use as accumulators in general arithmetic and logical oper ations, 15 of the 16 general registers are also used as base-address and index registers in address generation. In these cases, the registers are desig nated by a four-bit B field or X field in an instruction. A value of zero in the B or X field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index. FLOATING-POINT REGISTERS Four floating-point registers are avail able for floating-point operations. They are identified by the numbers 0, 2, 4, and 6 and are designated by a four- 2-4 System/370 Principles of Operation bit R field in floating-point instruc tions. Each floating-point register is 64 bits long and can contain either a short (32-bit) or a long (64-bit) floating-point operand. A short operand occupies the leftmost bit positions of a floating-point register. The rightmost portion of the register is ignored in operations that use short operands and remains unchanged in operations that produce short results. Two pairs of adjacent floating-point registers can be used for extended operands: registers 0 and 2, and registers 4 and 6. Each of these pairs, identified by the numbers 0 and 4, provides for a 128-bit format. CONTROL REGISTERS The CPU makes provisions for 16 control registers, each having 32 bit positions. The bit positions in the registers are assigned to particular facilities in the system, such as program-event recording, and are used either to specify that an operation can take place or to furnish special information required by the facility. The control registers are identified by the numbers 0-15 and are designated by four-bit R fields in the instructions LOAD CONTROL and STORE CONTROL. Multi ple control registers can be addressed by these instructions. VECTOR FACILITY Depending on the model, a vector facili ty may be provided as an extension of the CPU. When the vector facility is provided on a CPU, it functions as an integral part of that CPU. The func tions of the vector facility and its registers are described in the publica tion IBM System/370 Vector Operations, SA22-7125. Input/output (I/O) operations involve the transfer of information between main storage and an I/O device. I/O devices and their control units attach to chan nels, which control this data transfer.
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CHAPTER ~ STORAGE Storage Addressi ng .....•.....•.....•••••..••••..•.....•.•• 3-2 Storage Addressing with Extended Address Fields ..••... 3-3 Information Formats ....•................•....•.......... 3-3 Integral Boundaries ..............••........••........... 3-3 Byte-Oriented-Operand Facility ••..•.•••...••..••••...••. 3-5 Address Types .............•..•.••.•...••...•.•.•••...•••.• 3-5 Absolute Address ....•...•..••••...••.....•••..•....••. 3-5 Real Address ...........•.....•....•......•••.•.••.•.•. 3-5 Virtual Address ........•....••..•.....•...••..••..•... 3-5 Primary Virtual Address •...•..•.•.....•...•••.•••.•.•. 3-5 Secondary Virtual Address ..•••....•••...••••.••.•..•.. 3-6 Logi cal Address ....................................... 3-6 Instruction Address ....•....••.............•......•... 3-6 Effective Address ....••••...•••...•.•....••..•.•.•••.. 3-6 Storage Key ..........................••......•..••........ 3-6 Storage-Key 4K-Byte-Block Fac iIi ty •..........•..•.•••... 3-7 Storage Keys with Storage-Key 4K-Byte-Block Facility Not Installed ........••..........•.•••••.•.. 3-7 Storage Keys with Storage-Key 4K-Byte-Block Facility Installed ......•..........•.•.....••.••..... 3-7 Storage-Key-Exception Control .........•...•........... 3-7 Storage-Key-Instruction Extensions .........•......•.•... 3-7 Protection ...•..................•.....•......•...•....••.. 3-7 Key-Controlled Protection .....•.•.•..••...••.•.••.....•. 3-8 Segment Protection ........•.........•••.•.•••.••••...••. 3-9 low-Address Protection ..................•...••...•...••. 3-9 Reference Recording .........••.......•....••..•.•...•••.•. 3-10 Change Recording ........•.................••...•.....•.... 3-10 Prefixing .........................•...•...••.......•...... 3-11 Address Spaces .......•..............•...•...............•. 3-12 ASH Translation ...•.•....••.....•.•.•••.•...•.......•..... 3-13 ASH-Translation Controls ..•......•.........••...••.••••. 3-13 ASH-Translation Tables .............••.•....••.......••.. 3-14 ASH-First-Table Entries ...........•...•..••...•...•.•. 3-14 ASN-Second-Table Entries ..................•....•.•..•. 3-14 ASH-Translation Process ..••.•....••...•.•...•••.•.•...•. 3-15 ASH-First-Table Lookup ........•....................... 3-16 ASH-Second-Table lookup .•...........•.•.•...•.••...... 3-16 Recognition of Exceptions during ASH Translation ...... 3-17 ASH Authorization ...............•.....•.•.............•... 3-17 ASH-Authorization Controls ...•.•....••....•...•....••... 3-17 Control Register 4 ....•.....•....••••.•.•....••.•••.•. 3-17 ASN-Second-Table Entry ...........••......•...••..••... 3-17 Authority-Table Entries ...........•................... 3-18 ASH-Authorization Process •••••..•.••....•...•••.••••.••. 3-18 Authority-Table lookup •••.•..•..••....•••••••.•••.•••• 3-19 Recognition of Exceptions during ASH Authorization •.......•...•••...•..••...•..••••.••.••• 3-20 Dynamic Address Translation ..••....••••....•...•..••••.••• 3-20 Translation Control .•.••••••••••••..•••.•••••.•..••.•.•• 3-22 Translation Modes .••••...•....•.•••.•..••.•••.•..••..• 3-22 Control Register 0 •.•...•.......•••...•.••..•...••.... 3-23 Control Register 1 ..••..•.•.•.•.....•....•....•.••.•.. 3-24 Control Register 7 ..•••.••.••.•••••••.••••.••••••.•••. 3-24 Translation Tables •...•.••.••••....••••.•••••.••.••••..• 3-25 Segment-Table Entries ...•..•••..••••••..•.•.••.••.••.. 3-25 Page-Table Entries ..•..•...••.•.•••••....•..••.••••••• 3-26 Summary of Dynamic-Address-Translation Formats ••••.••••• 3-26 Translation Process ••.•.•.••..•••.••••••••.••••••••••••. 3-27 Effective Segment-Table Designation ••.••.•.•.••••••••. 3-27 Inspecti on of Control Regi ster 0 •••••......•••.....••. 3-30 Segment-Table lookup ••........•..•....•.............•. 3-30 Page-Table lookup •••.•.••.•••••••••••.•••••••••••••.•• 3-31 Formation of the Real Address ••••••••••••••••..•.••••. 3-31 Recognition of Exceptions during Translation •••••••••• 3-31 Translation-lookaside Buffer .•...•••..•..••..•••••.••••• 3-31 Use of the Translation-lookaside Buffer ••••••••••••••• 3-32 Modification of Translation Tables •••••••••••••••••••• 3-36 Chapter 3. Storage 3-1
Address Summary ••.•••••.••...•..•••••••••.••••.•...•.••••• 3-38 Addresses Translated .•••••.••...••..••......•......•.... 3-38 Handling of Addresses •.•.•...•..•••.•••••..•••.••...•.•. 3-39 Assigned Storage locations .........•••..•.•.......•....••. 3-41 This chapter discusses the represen tation of information in main storage, as well as addressing, protection, and reference and change recording. The aspects of addressing which are covered include the format of addresses, the concept of address spaces, the various types of addresses, and the manner in which one type of address is translated to another type of address. A list of permanently assigned storage locations appears at the end of the chapter. Main storage provides the system with directly addressable fast-access storage of data. Both data and programs must be loaded into main storage (from input devices) before they can be processed. Main storage may include one or more smaller faster-access buffer storages, sometimes called caches. A cache 1S usually physically associated with a CPU or an I/O processor. The effects, except on performance, of the physical construction and use of distinct storage media are not observable by the program. Fetching and storing of data by a CPU are not affected by any concurrent chan nel activity or by a concurrent refer ence to the same storage location by another CPU. When concurrent requests to a main-storage location occur, access normally is granted in a sequence that assigns highest priority to references by channels, the priority being rotated among CPUs. If a reference changes the contents of the location, any subsequent storage fetches obtain the new contents. Main storage may be volatile or nonvola tile. If it is volatile, the contents of main storage are not preserved when power is turned off. If it is nonvola tile, turning power off and then back on does not affect the contents of main storage, provided all CPUs are in the stopped state and no references are made to main storage when power is being turned off. In both types of main stor age, the contents of the storage key are not necessarily preserved when the power for main storage is turned off. Note: Because most references in this pUblication apply to virtual storage, the abbreviated term "storage" is often used in place of "virtual storage." The term "storage" may also be used in place of "main storage," "absolute storage," or "real storage" when the meaning is clear. The terms "main storage" and "absolute storage" are used to describe storage which is addressable by means of 3-2 System/370 Principles of Operation an absolute address. The terms describe fast-access storage, as opposed to auxiliary storage, such as provided by direct-access storage devices. "Real storage" is synonymous with "absolute storage" except for the effects of prefixing. STORAGE ADDRESSING Storage is viewed as a long horizontal string of bits. For most operations, accesses to storage proceed in a left to-right sequence. The string of bits is subdivided into units of eight bits. An eight-bit unit is called a byte, which is the basic building block of all information formats. Each byte location in storage is identi fied by a unique nonnegative integer, which 1S the address of that byte location or, simply, the byte address. Adjacent byte locations have consecutive addresses, starting with 0 on the left and proceeding in a left-to-right sequence. With the exception of those facilities described in "Storage Addressing with Extended Address Fields" below, addresses are 24-bit unsigned binary integers, which provide 16,777,216 (2 24 or 16M) byte addresses. The CPU performs address generation when it forms an operand or instruction address, or when it generates the address of a table entry from the appro priate table origin and index. It also performs address generation when it increments an address to access succes sive bytes of a field. Similarly, the channel performs address generation when it increments an address (1) to fetch a CCW, (2) to fetch an IDAW or (3) to transfer data. When, during address generation, an address is obtained that exceeds 224 -1, the carry out of the leftmost bit position of the address is ignored. This handling of an address of excessive size is called wraparound. The effect of wraparound is to make the sequence of addresses appear circular; that is, address 0 appears to follow the maximum byte address, 16,777,215. Address arithmetic and wraparound occur before transformation, if any, of the address by dynamic address translation or prefixing. With a 16M-byte storage, information may be located partially in