Programming Notes
1 • Examples of the use of the COMPARE LOGICAL instruction are given in
Appendix A.
2. COMPARE LOGICAL treats all bits of
each operand alike as part of a field of unstructured logical data.
For COMPARE LOGICAL (CLC), the
comparison may extend to field
lengths of 256 bytes. COMPARE LOGICAL CHARACTERS UNDER MASK
o 8 12 16 20 31
The first operand is compared with the
second operand under control of a mask,
and the result is indicated in the
condition code.
The contents of the M3 field are used as
a mask. These four bits, left to right,
correspond one for one with the four
bytes, left to right, of general regis­
ter R t • The byte positions correspond­
ing to ones in the mask are considered
as a contiguous field and are compared
with the second operand. The second
operand is a contiguous field in storage, starting at the second-operand
address and equal in length to the
number of ones in the mask. The bytes in the general register corresponding to
zeros in the mask do not participate in the operation.
The comparison proceeds left to right,
byte by byte, and ends as soon as an inequality is found or the end of the
fields is reached.
When the mask is not zero, exceptions
associated with storage-operand access
are recognized for no more than the
number of bytes specified by the mask.
Access exceptions mayor may not be
recognized for the portion of a storage
operand to the right of the first
unequal byte. When the mask is zero,
access exceptions are recognized for one
byte at the second-operand address.
Resulting Condition Code:
o
1
2
3 Operands equal, or mask bits
all zeros
First operand low
First operand high
Program Exceptions:
Access (fetch, operand 2)
Programming Note
An example of the use of the LOGICAL CHARACTERS UNDER MASK
tion is given in Appendix A. COMPARE LOGICAL LONG CLCL [RR] 'OF' o 8 12 15 COMPARE instruc-
The first operand is compared with the
second operand, and the result is indi­
cated in the condition code. The short­
er operand is considered to be extended
on the right with padding bytes.
The Rt and R2 fields each
even-odd pair of general
must designate an
register; otherwise, a
exception is recognized.
designate an
registers and
even-numbered
specification
The location of the leftmost byte of the
first operand and second operand is
designated by bits 8-31 of general
registers Rt and R
2
, respectively. The
number of bytes in the first-operand and
second-operand locations is specified by
bits 8-31 of general registers Rt + 1
and R2 + 1, respectively. Bit positions 0-7 of general register R2 + 1 contain
the padding byte. The contents of bit
positions 0-7 of general registers Rt,
R21 and Rt + 1 are ignored.
The contents of the registers just
described are as follows:
R t 1////////1 First-Operand Address
o 8 31 \////////1 First-Operand Length
o 8 31
////////// Second-Operand Address/
o 8 31
Pad Second-Operand Length
o 8 31
Chapter 7. General Instructions 7-15

The comparison proceeds left to right,
byte by byte, and ends as soon as an
inequality is found or the end of the
longer operand is reached. If the oper­
ands are not of the same length, the
shorter operand is considered to be
extended on the right with the appropri­
ate number of padding bytes.
If both operands are of zero length, the
operands are considered to be equal.
The execution of the instruction is
interruptible. When an interruption
occurs, other than one that causes
termination, the contents of general
registers R! + 1 and R2 + 1 are decre­
mented by the number of bytes compared, and the contents of general registers R!
and R2 are incremented by the same
number, so that the instruction, when
reexecuted, resumes at the point of
interruption. The leftmost bits which
are not part of the address in general
registers Rt and R2 are set to zeros;
the contents of bit positions 0-7 of
general registers Rt + 1 and R2 + 1
remain unchanged; and the condition code
is unpredictable. If the operation is
interrupted after the shorter operand
has been exhausted, the length field
pertaining to the shorter operand is
zero, and its address is updated accord­
ingly.
If the operation ends because of an
inequality, the address fields in gener­
al registers Rt and R2 at completion
identify the first unequal byte in each
operand. The lengths in bit positions
8-31 of general registers Rt + 1 and R2 + 1 are decremented by the number of
bytes that were equal, unless the
inequality occurred with the padding
byte, in which case the length field for the shorter operand is set to zero. The
addresses in general registers Rt and R2 are incremented by the amounts by which
the corresponding length fields were
reduced.
If the two operands, including the
padding byte, if necessary, are equal,
both length fields are made zero at completion, and the addresses are incre­
mented by the corresponding operand­
length values.
At the completion of the operation, the
leftmost bits which are not part of the
address in general registers R! and R2 are set to zeros, including the case
when one or both of the initial length
values are zero. The contents of bit
positions 0-7 of general registers Rl + 1 and R2 + 1 remain unchanged.
Access exceptions for the portion of a
storage operand to the right of the
first unequal byte mayor may not be
recognized. For operands longer than 2K
bytes, access exceptions are not recog­
nized more than 2K bytes beyond the byte
being processed. Access exceptions are
7-16 System/370 Principles of Operation
not indicated for locations more than 2K
bytes beyond the first unequal byte.
When the length of an operand is zero,
no access exceptions are recognized for
that operand. Access exceptions are not
recognized for an operand if the R field
associated with that operand is odd.
Resulting Condition Code: o Operands equal, or both zero
length
1 First operand low
2 First operand high
3 Program Exceptions:
Access (fetch, operands 1 and 2)
Specification
1. An example of the use of the COMPARE LOGICAL LONG instruction is
given in Appendix A.
2. When the Rt and R2 fields are the
same, the operation proceeds in the
same way as when two distinct pairs
of registers having the same
contents are specified, and, in the
absence of dynamic modification of
the operand area by another CPU or
by a channel, condition code 0 is
set. However, it is unpredictable
whether access exceptions are
recognized for the operand since
the operation can be completed
without storage being accessed.
3. Other programming notes concerning
interruptible instructions are
included in the section "Interrup­
tible Instructions" in Chapter 5, "Program Execution." 4. Special precautions should be taken
when COMPARE LOGICAL LONG is made
the target of EXECUTE. See the
programming note concerning inter­
ruptible instructions under EXECUTE. CONVERT TO BINARY o 8 12 16 20 31
The second operand is changed from deci­
mal to binary, and the result is placed
at the first-operand location.