Emergency signal
External call
TOO-clock sync check Clock comparator CPU timer Service signal
The interval timer, interrupt key, and
the external signals 2-7 are of equal
priority; if more than one of these
conditions is pending and allowed, the
conditions are indicated concurrently.
All other requests are honored one at a
time. When more than one emergency­ signal request exists at a time or when
more than one malfunction-alert request
exists at a time, the request associated
with the smallest CPU address is honored
first. CLOCK COMPARATOR An interruption request for the clock
comparator exists whenever either of the
following conditions is met:
1. The TOO clock is in the set or
not-set state, and the value of the
clock comparator is less than the
value in the compared portion of
the TOO clock, both compare values
being considered unsigned binary
integers.
2. The clock comparator is installed,
and the TOO clock is in the error
or not-operational state.
If the condition responsible for the
request is removed before the request is
honored, the request does not remain
pending, and no interruption occurs.
Conversely, the request is not cleared
by the interruption, and, if the condi­
tion persists, more than one
interruption may result from a single
occurrence of the condition.
When the TOO clock accessed by a CPU is
set or changes state, interruption
conditions, if any, that are due to the
clock comparator mayor may not be
recognized for up to 1.048576 seconds
after the change.
The subclass-mask bit is in bit position 20 of control register O. This bit is initialized to zero.
The clock-comparator condition is indi­
cated by an external-interruption code
of 1004 hex. CPU TIMER
An interruption request
timer exists whenever
for the CPU the CPU-timer value is negative (bit 0 of the CPU timer is one). If the value is made
positive before the request is honored,
the request does not remain pending, and
no interruption occurs. Conversely, the request is not cleared by the inter­
ruption, and, if the condition persists,
more than one interruption may occur
from a single occurrence of the condi­
tion.
When the TOO clock accessed by a CPU is set or changes state, interruption
conditions, if any, that are due to the CPU timer mayor may not be recognized
for up to 1.048576 seconds after the
change.
The subclass-mask bit is in bit position
21 of control register O. This bit is
initialized to zero.
The CPU-timer condition is indicated by an external-interruption code of 1005 hex. EMERGENCY SIGNAL An interruption request for an emergency
signal is generated when the CPU accepts
the emergency-signal order specified by a SIGNAL PROCESSOR instruction address­
ing this CPU. The instruction may have
been executed by this CPU or by another CPU in the configuration. The request
is preserved and remains pending in the
receiving CPU until it is cleared. The
pending request is cleared when it caus­
es an interruption and by CPU reset.
Facilities are provided for holding a
separate emergency-signal request pend­
ing in the receiving CPU for each CPU in
the configuration, including the receiv­
ing CPU itself.
The subclass-mask bit is in bit position
17 of control register o. This bit is
initialized to zero.
The emergency-signal condition is indi­
cated by an external-interruption code
of 1201 hex. The address of the CPU that executed the SIGNAL PROCESSOR instruction is stored at real locations
132-133.
EXTERNAL CALL An interruption request for an external
call is generated when the CPU accepts
the external-call order specified by a SIGNAL PROCESSOR instruction addressing
this CPU. The instruction may have been
executed by this CPU or by another CPU in the configuration. The request is
preserved and remains pending in the
receiving CPU until it is cleared. The Chapter 6. Interruptions 6-11

pending request is cleared when it caus­
es an interruption and by CPU reset. Only one external-call request, along
with the processor address, may be held
pending in a CPU at a time.
The subclass-mask bit is in bit position
18 of control register O. This bit is initialized to zero.
The external-call condition is indicated
by an external-interruption code of 1202 hex. The address of the CPU that
executed the SIGNAL PROCESSOR instruc­
tion is stored at real locations
132-133.
EXTERNAL SIGNAL An interruption request for an external
signal is generated when a signal is received on one or more of the signal-in
lines. Up to six signal-in lines may be
connected, providing for external signal
2 through external signal 7. The
request is preserved and remains pending in the CPU until it is cleared. The
pending request is cleared when it caus­
es an interruption and by CPU reset. Facilities are provided for holding a separate external-signal request pending
for each of the six lines.
All external signals are subject to
control by the subclass-mask bit in bit
position 26 of control register o. This
bit is initialized to one.
External signals 2-7 are indicated by
setting to one interruption-code bits 10-15, respectively. Bits 0-7 are set
to zeros, and bits 8 and 9 are set to
zeros unless set to ones for other
conditions that are concurrently indi­
cated. Programming Notes
1.
2.
External
of I/O tions.
signaling is independent
operations and interrup-
The pattern presented in bit posi­
tions 10-15 of the interruption
code depends on the pattern
received before the interruption
occurs. Because of circuit skew,
all simultaneously generated
external signals do not necessarily
arrive at the same time, and some
may not be included in the inter­
ruption code for the external
interruption resulting from the
earliest signals. These late
signals, if not included in the
6-12 System/370 Principles of Operation interruption code, cause another
interruption to occur. INTERRUPT KEY
An interruption request for the inter­
rupt key is generated when the operator
activates that key. The request is
preserved and remains pending in the CPU until it is cleared. The pending
request is cleared when it causes an
interruption and by CPU reset.
When the interrupt key is activated
while the CPU is in the load state, it
depends on the model whether an inter­
ruption request is generated or the
condition is lost.
The subclass-mask bit is in bit position
25 of control register O. This bit is initialized to one.
The interrupt-key condition is indicated
by setting bit 9 in the interruption
code to one and by setting bits 0-7 to
zeros. Bits 8 and 10-15 are zeros
unless set to ones for other conditions
that are concurrently indicated.
INTERVAL TIMER
An interruption request for the interval
timer is generated when the interval
timer is decremented from a positive
number or zero to a negative number.
The request is preserved and remains
pending in the CPU until it is cleared.
The pending request is cleared when it
causes an interruption and by CPU reset.
When the TOO clock accessed by a CPU is
set or changes state, interrupt ion
conditions, if any, that are due to the
interval timer mayor may not be recog­
nized for up to 1.048576 seconds after
the change.
The subclass-mask bit is in bit position
24 of control register O. This bit is
initialized to one.
The interval-timer condition is indi­
cated by setting bit 8 in the inter­
ruption code to one and by setting bits 0-7 to zeros. Bits 9-15 are zeros
unless set to ones for other conditions
that are concurrently indicated. MALFUNCTION ALERT
An interruption request for a malfunc­
tion alert is generated when another CPU in the configuration enters the check­
stop state or loses power. The request