PROGRAM TRANSFER PT [RREl
'B228'
o 16 24 28 31
The contents of general register Rt are
used as the new values for the PSW-key mask, the PASN, and the SASN. The
contents of general register R2 are used
as the new values for the problem-state
bit and instruction address in the
current PSW. Bits 16-23
ignored.
of the
General registers Rt
following format:
R t PSW-Key Mask
o
instruction are
and R2 have the ASN 16 31
R2 1000000001 Instruction Address Ipi o 8 31
When the contents of bit positions 16-31
of general register Rt are equal to the
current PASN, the operation is called PROGRAM TRANSFER to current primary
(PT-cp); when the fields are not equal,
the operation is called PROGRAM TRANSFER with space switching (PT-ss).
The contents of general register R2 are used to update the problem-state bit and
the instruction address of the current PSW. Bit 31 of general register R2 is
placed in the problem-state bit
position, PSW bit position 15, unless
the operation would cause PSW bit 15 to
change from one to zero (problem state
to supervisor state). If such a change
would occur, a privileged-operation
exception is recognized. Bits 8-30 of
general register R2 replace the instruc­
tion address, bits 40-62, of the current PSW. Bit 63 of the PSW is set to zero.
Bits 0-15 of general register Rt are
ANDed with the PSW-key mask, bits 0-15 of control register 3, and the result
replaces the contents of the PSW-key mask.
In both the PT-ss and PT-cp
instructions, the ASN specified by bits
16-31 of general register Rt replaces
the SASN in control register 3, and the SSTD in control register 7 is replaced
by the final contents of control regis­
ter 1. PROGRAM TRANSFER to Current Primary
(PT-cp)
The PROGRAM TRANSFER to current primary
(PT-cp) operation is depicted in part 1
of the figure "Execution of PROGRAM TRANSFER." On a PT-cp operation, the
operation is completed when the common
portion of the PROGRAM TRANSFER opera­
tion, described above, is completed.
The authorization index, PASN, primary STD, and linkage-table designation are
not changed by PT-cp. PROGRAM TRANSFER with Space Switching (PT-ss) If the ASN in bits 16-31 of general
register Rt is not equal to the current PASN, a PROGRAM TRANSFER with space
switching (PT-ss) is specified, and the ASN is translated by means of a two­
level table lookup.
The PT-5s operation is depicted in parts
1 and 2 of the figure "Execution of PROGRAM TRANSFER." The PT-ss operation
is completed as follows:
For a PT-ss, the contents of bit posi­
tions 16-31 of general register Rt are
used as an ASN, which is translated by
means of a two-level table lookup.
Bits 16-25 of general register Rt are a 10-bit AFX which is used to select an
entry from the ASH first table. Bits
26-31 are a six-bit ASX which is used to
select an entry from the ASN second
table. The ASN table-lookup process is
described in the section "ASN Trans­
lation" in Chapter 3, "Storage." The
exceptions associated with ASN trans­
lation are collectively called "ASN­ translation exceptions." These
exceptions and their priority are
described in Chapter 6, "Interruptions."
The authority-table orlgln from the
ASN-second-table entry is used as the
base for a third table lookup. The
current authorization index, bits 0-15 of control register 4, is used, after it
has been checked against the authority­
table length, as the index to locate the
entry in the authority table. The
authority-table lookup is described in
the section "ASN Authorization" in Chap­ ter 3, "Storage."
The PT-ss operation is completed by
placing bits 64-95 of the ASN-second­
table entry in both the PSTD and SSTD, bit positions 0-31 of control registers
1 and 7, respectively. The contents of
bit positions 32-47 of the ASN-second­
table entry are placed in the authoriza­
tion index, bit positions 0-15 of
control register 4. The contents of bit
positions 96-127 of the ASN-second-table Chapter 10. Control Instructions 10-31

entry are placed in the LTD, bit posi­
tions 0-31 of control register 5. The ASH, bits 16-31 of general register Rtl is placed in the SASH and PASH, bit
positions 16-31 of control registers 3 and 4.
For both the PT-cp and PT-ss operations,
a serialization and checkpoint-synchron­
ization function is performed before the
operation begins and again after the
operation is completed.
Special Conditions The instruction can be executed only
when the CPU is in primary-space mode
and the subsystem-linkage control, bit 0 of control register 5, is one. If the CPU is in real mode or secondary-space
mode, or if the subsystem-linkage
control is zero, a special-operation
exception is recognized.
Bit 31 of general register R2 is placed
in the problem-state bit position, PSW
bit position 15, unless the operation
would cause PSW bit 15 to change from
one to zero (problem state to supervisor
state). If such a change would occur, a
privileged-operation exception is recog­
nized.
The instruction is completed only if
bits 0-7 of general register R2 are all
zeros; if not, a specification exception
is recognized.
In addition to the above requirements,
when a PT-ss instruction is specified, 10-32 System/370 Principles of Operation
the ASH-translation control, bit 12 of
control register 14, must be one; other­
wise, a special-operation exception is
recognized.
When, for PT-ss, the space-switch­
event-control bit, bit 31 of control
register 1, is one either before or
after the execution of the instruction,
a space-switch-event program inter­
ruption occurs after the operation is
completed. A space-switch-event program
interruption also occurs after the
completion of a PT-ss operation if a PER
event is reported.
The operation is suppressed on all
addressing exceptions.
The priority of recognition of program
exceptions for the instruction is shown
in the figure "Priority of Execution: PROGRAM TRAHSFER." Condition Code: unchanged.
Program Exceptions:
The code remains
Addressing (authority-table entry,
PT-ss only) ASH translation (PT-ss only)
Operation (if the dual-address-
space facility is not
installed)
Primary authority (PT-s5 only)
Privileged operation (attempt to
set the supervisor state when
in the problem state)
Space-switch event (PT-ss only)
Special operation
Specification
Trace