is performed, the CPU starts operating
at normal speed. When the rate control
is set to the instruction-step position
and the wait-state bit is zero, one
instruction or, for interruptible
instructions, one unit of operation is
executed, and all pending allowed inter­
ruptions are taken before the CPU returns to the stopped state. When the
rate control is set to the instruction­
step position and the wait-state bit is one, the start function causes no
instruction to be executed, but all
pending allowed interruptions are taken
before the CPU returns to the stopped
state.
LOAD STATE The CPU enters the load state when the load-normal or load-clear key ;s acti­ vated. (See the section "Initial
Program loading" in this chapter.) If
the initial-program-Ioading operation is completed successfully, the CPU changes
from the lo~d state to the operating
state, provided the rate control is set
to the process position; if the rate
control is set to the instruction-step
position, the CPU changes from the load
state to the stopped state.
CHECK-STOP STATE
The check-stop state, which the CPU enters on certain types of machine malfunction, is described in Chapter 11, nl1achine-Check Hundling." The CPU leaves the check-stop state when CPU reset is perfor~ed. ProqramminQ Notes 1. Except for the relationship between execution time and real time, the execution of a program is not affected by stopping the CPU. 2. When, because of a m~chine malfunc­ ~lon, an invalid address in the
prefix register, or an incomplete
READ DIRECT instruction, the CPU is unable to end the execution of an
instruction, the stop function is
ineffective, and a reset function has to be invoked instead. A simi­ lar situation occurs when an unending string of interruptions results from a PSW with a PSW-format error of the type that
is recognized early, or from a
persistent interruption condition,
such as one due to the CPU timer.
3. Pending I/O operations may be
initiated, and active I/O oper­
ations continue to suspension or
completion, after the CPU enters
the stopped state. The inter-
ruption conditions due to
suspension or completion of I/O
operations remain pending when the
CPU is in the stopped state.
PROGRAM-STATUS WORD
The current program-status word (PSW) in
the CPU contains information required
for the execution of the currently active program. The PSW is 64 bits in
length and includes the instruction
address, condition code, and other
control fields. In general, the PSW is used to control instruction sequencing
and to hold and indicate much of the
status of the CPU in relation to the
program currently being executed. Addi­
tional control and status information is
contained in control registers and
permanently assigned storage locations.
The status of the CPU can be changed by
loading a new PSW or part of a PSW. Control is switched during an inter­
ruption of the CPU by storing the
current PSW, so as to preserve the
status of the CPU, and then loading a new PSL~. Execution of LOAD PSW, or the successful
conclusion of the initial-progrDm­ loading sequence, introduces a new PSW. The instruction address is updated by sequential instruction Qxecution and replaced by successful branches. Other instructions are provided which operate on a portion of the PSW. The figure "Operati ons on PSL~ Fi eids" sumr:'lari .::es these instructions. A new or modified PSW becomes active (that is, tha information introduced
into the current PSW assumes control over the CPU) when the interruption or
the execution of an instruction that changes the PSW is co~pleted. The interruption for PER associated with an instruction th~t changes the PSW occurs
under control of the PER mask that is effective at the beginning of the opera­ tion. Bits 0-7 of the PSW are collectively
referred to as the system mask.
Chapter 4. Control 4-3

System Mask (PSW Bits 0-7) PSW Key (PSW Bits 8-11) Condition Code and Program Mask
l Problem State (PSW Bit 15)
Address­ Space Control2 Instruction BRANCH AND LINK INSERT PSW KEY
INSERT ADDRESS SPACE CONTROL PROGRAM CALL PROGRAM TRANSFER SET ADDRESS SPACE CONTROL SET PROGRAM MASK SET PSW KEY FROM ADDRESS SET SYSTEM MASK STORE THEN AND SYSTEM MASK STORE THEN OR SYSTEM
MASK
Explanation: Saved Set Saved No No No
No No Yes
No No No
No No No
No No No
No No No No No No
No No No No Yes No
Yes ANDs No Yes ORs No Set No
No
No
No
No
No
No
Yes No No No Saved Yes
No
No
No No No
No
No
No
No No Set No No
No
No
No
No
Yes
No
No
No
No Saved No
No No Yes No No No No No No No Set Saved No No No No No Yes
Yes No Yes
l No
No No
No No
No No
No No
No No
No No Set No
No
No
No
No
Yes
No
No
No
No
No
1 PSW bits 18-23 in the EC mode; PSW bits 34-39 in the BC mode.
Bit 16 of the EC-mode PSW. 3 Cannot be changed from one to zero.
ANDs The logical AND of the immediate field in the instruction and the current
system mask replaces the current system mask. ORs The logical OR of the immediate field in the instruction and the current
system m~sk replaces the current system mask. Operations on PSW Fields EC AND BC MODES Two control modes are provided for the formatting and use of control and status
information: the extended-control (EC) mode and the basic-control (BC) mode. Certain functions available in the EC mode, such as PER, are not available in
the BC mode. The mode currently in effect is specified by PSW bit 12. Bit
12 is one for the EC mode and zero for
the BC mode.
Bit 6 of the PSW, in both the BC and EC mode3, is the summary-mask bit for con~rolling I/O interruptions. In addi­ tion, I/O interruptions can be
controlled individually for up to 32 channels. In the EC mode, the individ­
ual control is provided by the 32 mask
bits in control register 2, and the
summary-mask bit in the PSW applies to
all 32 channels. In the BC mode, chan­
nels 6 and up are individually
controlled by the corresponding bits of
control register 2, as well as the
summary-mask bit, bit 6 of the PSW. In
the BC mode, channels 0-5 are controlled separately by bits 0-5 of the PSW and
4-4 System/370 Principles of Operation are not subject to the summary mask or
to mask bits in control register 2.
When interruptions occur in the EC mode,
the interruption code and instruction­
length code are stored at various perma­
nently assigned storage locations
according to the class of interruptions.
In the BC mode, the interruption code
(for all except machine-check inter­
ruptions) and instruction-length code are placed in the old PSW. The program-mask and fields in the PSW are
different bit positions
control modes.
condition-code
allocated to
in the two
The instruction INSERT STORAGE KEY
provides the reference and change bits when in the EC mode but produces zeros in the corresponding bit positions when in the BC mode. The instruction INSERT STORAGE KEY EXTENDED provides the refer­ ence and change bits in both the EC and BC modes.
The following instructions, all of which are associated with the DAS facility,
cause a program interruption for