Information Stored (Fetched) Old PSW New PSW (fetched)
Machine-cheek-interruption code
Register-save areas CPU timer Clock comparator
Floating-point registers 0, 2, 4, 6
General registers 0-15 Control registers 0-15
Extended interruption information
External-damage code
Failing-storage address
Region code
logout areas
Fixed logout
Machine-check extended logout (MCEL) Explanation: * All locations are in real storage.
Starting Length
Location* in Bytes
48
112
232
216
224
352
384
448
244
248
252
256
Note 1
8
8
8
8
8 32 64
64
4
4
4
96
Note 2
1. The starting location of the MCEL is determined by the MCEL address in control register 15.
2. The length of the MCEL is model-dependent.
Machine-Cheek-Interruption locations
If the machine-cheek-interruption code
cannot be stored successfully or the new PSW cannot be fetched successfully, the CPU enters the check-stop state if the
check-stop-control bit is one.
A repressible machine-check condition
can initiate a machine-check inter­
ruption only if both PSW bit 13 is one
and the associated subclass mask bit in
control register 14 is also one. When
it occurs, the interruption does not
terminate the execution of the current
instruction; the interruption is taken
at a normal point of interruption, and
no program or supervisor-call inter­
ruptions are eliminated. If the machine
check occurs during the execution of a
machine function, such as a CPU-timer update, the machine-check interruption
takes place after the machine function
has been completed.
When the CPU is disabled for a partic­
ular repressible machine-check
condition, the condition remains
pending. Depending on the model and the
condition, multiple repressible condi­
tions may be held pending for a
particular subclass, or only one condi­
tion may be held pending for a
particular subclass, regardless of the
number of conditions that may have been
detected for that subclass. When multi­
ple external-damage conditions occur,
each condition is retained.
When a repressible machine-check inter­
ruption occurs because the interruption
condition is in a subclass for which the CPU is enabled, pending conditions in
other subclasses may also be indicated
in the same interruption code, even
though the CPU is disabled for those
subclasses. All indicated conditions
are then cleared.
If a machine check which is to be
reported as a system-recovery condition
is detected during the execution of the
interruption procedure due to a previous
machine-check condition, the system­
recovery condition may be combined with
the other conditions, discarded, or held
pending.
An exigent machine-check condition can
cause a machine-check interruption only
when PSW bit 13 is one. When a nullify­
ing exigent condition causes a machine­
check interruption, the interruption is
taken at a normal point of interruption.
When a terminating exigent condition
causes a machine-check interruption, the
interruption terminates the execution of
the current instruction and may elimi­
nate the program and supervisor-call
interruptions, if any, that would have
occurred if execution had continued.
Proper execution of the interruption
sequence, including the storing of the
old PSW and other information, depends
on the nature of the malfunction. When an exigent machine-check condition
occurs during the execution of a machine
function, such as a CPU-timer update,
the sequence is not necessarily
completed. Chapter 11. Machine-Check Handling 11-13

When PSW bit 13 is zero and an exigent
machine-check condition is generated,
subsequent action depends on the state
of the check-stop-control bit, bit 0 of
control register 14. When the check­
stop-control bit is zero, the machine­
check condition is held pending, and an
attempt is made to complete the
execution of the current instruction and
to proceed with the next sequential
instruction. When the check-stop­
control bit is one, processing stops
immediately, and the CPU enters the
check-stop state. Depending on the
model and the severity of the error, the
CPU may enter the check-stop state even
when the check-stop-control bit is zero.
Similarly, if, during the execution of
an interruption due to one exigent
machine-check condition, another exigent
machine check is detected, the subse­
quent action depends on the state of the
check-stop-control bit. If the 'check­
stop-control bit is one, the CPU enters
the check-stop state; if the bit is
zero, an attempt is made to proceed with
the condition held pending for subse­
quent interruption. If an exigent
machine check is detected during an
interruption due to a repressible
machine-check condition, system damage
is reported.
Exigent machine-check conditions held
pending while the check-stop-control bit
is zero remain pending and do not cause
the CPU to enter the check-stop state if
the check-stop-control bit is subse­
quently set to one.
Machine-cheek-interruption conditions
are handled in the same manner regard­
less of whether the wait-state bit in
the PSW is one or zero: a machine-check
condition causes an interruption if the
CPU is enabled for that condition.
Machine checks which occur while the
rate control is set to the instruction­
step position are handled in the same
manner as when the control is set to the
process position; that is, recovery
mechanisms are active, and logout and
machine-check interruptions occur when
allowed. Machine checks occurring
during a manual operation may be indi­
cated to the operator, may generate a
system-recovery condition, may be
reported as an external secondary
report, may result in system damage, or
may cause a check stop, depending on the
model.
Every reasonable attempt is made to
limit the side effects of any machine
check and the associated interruption.
Normally, interruptions, as well as the
progress of I/O operations, remain unaf­
fected. The malfunction, however, may
affect these activities, and, if the
currently active PSW has bit 13 set to
one, the machine-check interruption will
indicate the total extent of the damage
11-14 System/370 Principles of Operation caused, and not just the damage which
originated the condition. POINT OF INTERRUPTION The point in the processing which is
indicated by the interruption and used
as a reference point by the machine to
determine and indicate the validity of
the status stored is referred to as the
point of interruption.
Because of the checkpoint capability in
models with CPU retry, the interruption
resulting from an exigent machine­
check-interruption condition may indi­
cate a point 1n the CPU processing
sequence which is logically prior to the
error. Additionally, the model may have
some choice as to which point in the CPU processing sequence the interruption is
indicated, and, in some cases, the
status which can be indicated as valid
depends on the point chosen. Only certain points in the processing
may be used as a point of interruption.
For repressible machine-check inter­
ruptions, the point of interruption must
be after one unit of operation is
completed and any associated program or
supervisor-call interruption is taken,
and before the next unit of operation is
begun.
Exigent machine-check conditions for
instruction sequences are those in which
damage has or would have occurred to the
instruction stream. Thus, the damage
can normally be associated with a point
part way though an instruction, and this
point is called the point of damage. In
some cases there may be one or more
instructions separating the point of
damage and the point of interruption,
and the processing associated with one
or more instructions may be damaged.
When the point of interruption is a
point prior to the point of damage due
to a nullifiable exigent machine-check
condition, the point of interruption can
be only at the same points as for
repressible machine-check conditions.
Exigent machine-check conditions which
are delayed (disallowed and presented
later when allowed) can be presented
only at the same points of interruption
as repressible machine-check conditions. When a terminating exigent machine-check
condition is not delayed, the point of
interruption may also be after the unit
of operation is completed but before any
associated program or supervisor-call
interruption occurs. In this case, a
valid PSW instruction address is defined
as that which would have been stored in
the old PSW for the program or
supervisor-call interruption. Since the
operation has been terminated, the
values in the result fields, other than