and the address of the last
instruction executed cannot be
calculated using the one appearing
in the program old PSW. For situation f, the instruction
address in the PSW has not been
replaced, but the corresponding
real address after the change may
be different.
2. The instruction-length code (IlC) is redundant when a PER event is
indicated since the PER address in
the word at real location 152 iden­
tifies the instruction causing the
interruption (or the EXECUTE instruction, as appropriate). Similarly, the ILC is redundant
when the operation is nullified,
since in this case the instruction
address in the PSW is not incre­
mented. If the IlC value is
required in this case, it can be
derived from the operation code of
the instruction identified by the
old PSW. EXCEPTIONS ASSOCIATED WITH THE PSW Exceptions associated with erroneous
information in the current PSW may be
recognized when the information is
introduced into the PSW or may be recog­
nized as part of the execution of the
next instruction. Errors in the PSW which are specification-exception condi­
tions are called PSW-format errors.
Early Exception Recognition
For the following error conditions, a program interruption for a specification
exception occurs immediately after the PSW becomes active: • The EC mode is specified
12 is one) in a CPU that
have the translation
installed. (PSW bit
does not
facility • Bit position 16 of an EC-mode PSW is one, and DAS is not installed. • A one is introduced into an unas­
signed bit position of an EC-mode PSW (that is, any of bit positions 0, 2-4, 17, or 24-39).
The interruption occurs regardless of
whether the wait state is specified. If
the invalid PSW causes the CPU to become
enabled for a pending I/O, external, or
machine-check interruption, the program
interruption occurs instead, and the
pending interruption is subject to the
mask bits of the new PSW introduced by
the program interruption. If the EC mode is not present, bits 0-15 and 34-63
of the invalid PSW are stored unchanged
in the corresponding bit positions of
the program old PSW, and the inter­
ruption code and instruction-length code
are stored in bit positions 16-33 of the
program old PSW. When the execution of LOAD PSW or an
interruption introduces a PSW with one
of the above error conditions, the
instruction-length code is set to 0, and
the newly introduced PSW' except for the
interruption code and the instruction­
length code in the BC mode, is stored
unmodified as the old PSW. When one of
the above error conditions is introduced
by execution of SET SYSTEM MASK or STORE THEN OR SYSTEM MASK, the instruction­
length code is set to 2, and the
instruction address 1S incremented by 4. The PSW containing the invalid value
introduced into the system-mask field ;s
stored as the old PSW. When a PSW with one of the above error
conditions is introduced during initial
program loading, the loading sequence is
not completed, and the load indicator
remains on.
late Exception Recognition
For the following conditions, the excep­
tion is recognized as part of the
execution of the next instruction: • • A specification exception is recog­
nized due to an odd instruction
address in the PSW (PSW bit 63 is
one).
An access exception (addressing,
page-translation, protection, seg­
ment-translation, or translation­
specification) is associated with
the location designated by the
instruction address or with the
location of the second or third
halfword of the instruction start­
ing at the designated instruction
address.
The instruction-length code and instruc­
tion address stored in the program old PSW under these conditions are discussed
in the section "IlC on Instruction­
Fetching Exceptions" in this chapter.
If an I/O, external, or machine-check­
interruption condition is pending and
the PSW causes the CPU to be enabled for
that condition, the corresponding inter­
ruption occurs, and the PSW is not
inspected for exceptions which are
recognized late. Similarly, a PSW spec­
ifying the wait state is not inspected
for exceptions which are recognized
late. Chapter 6. Interruptions 6-9

Programming Notes 1. The execution of LOAD ADDRESS SPACE PARAMETERS, LOAD PSW, PROGRAM CALL, PROGRAM TRANSFER, SET PREFIX, SET SECONDARY ASN, SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and STORE THEN OR SYSTEM MASK is
suppressed on an addressing or
protection exception, and hence the program old PSW provides informa­
tion concerning the program causing
the exception.
2. When the first halfword of an
instruction can be fetched but an
access exception is recognized on
fetching the second or third half­
word, the ILC is not necessarily related to the operation code.
3. If the new PSW introduced by an
interruption contains a PSW-format error, a string of interruptions
may occur. (See the section "Pri­ ority of Interruptions" in this chapter.)
EXTERNAL INTERRUPTION The external interruption provides a
means by which the CPU responds to vari­ ous signals originating from either inside or outside the configuration.
An external interruption causes the old PSW to be stored at real location 24 and
a new PSW to be fetched from real
location 88. The source of the interruption is iden­
tified in the interruption code. When
the old PSW specifies the EC mode, the
interruption code is stored at real
locations 134-135. When the old PSW specifies the BC mode, the interruption
code is placed in bit positions 16-31 of
the old PSW, and the instruction-length
code is unpredictable.
Additionally, for the malfunction-alert,
emergency-signal, and external-call
conditions, a 16-bit CPU address is associated with the source of the inter­
ruption and is stored at real locations
132-133 in both the EC and BC modes. When the CPU address is stored, bit 6 of
the interruption code is set to one.
For all other conditions, no CPU address is stored, and bit 6 of the interruption
code is set to zero. When bit 6 is zero
and the old PSW specifies the EC mode, zeros are stored at real locations
132-133. When bit 6 is zero and the old PSW specifies the BC mode, the contents
of real locations 132-133 remain unchanged.
For the service-signal interruption, a
32-bit parameter is associated with the 6-10 System/370 Principles of Operation interruption and is stored at real
locations 128-131 in both the EC and BC modes. Bit 2 of the external­
interruption code indicates that a
parameter has been stored. When bit 2 is zero, the contents of real locations
128-131 remain unchanged.
External-interruption conditions are of
two types: those for which an
interruption-request condition is held
pending, and those for which the condi­
tion directly requests the interruption.
Clock comparator, CPU timer, and TOD­ clock sync check are conditions which
directly request external interruptions.
If a condition which directly requests
an external interruption is removed
before the request is honored, the
request does not remain pending, and no
interruption occurs. Conversely, the
request is not cleared by the inter­
ruption, and if the condition persists,
more than one interruption may result
from a single occurrence of the c~ndi­ tion.
When several interruption requests for a
single source are generated before the
interruption occurs, and the inter­
ruption condition is of the type which
is held pending, only one request for
that source is preserved and remains
pending.
An external interruption for a partic­
ular source can occur only when the CPU is enabled for interruption by that
source. The external interruption
occurs at the completion of a unit of
operation. The external mask, PSW bit
7, and external subclass-mask bits in
control register 0 control whether the CPU is enabled for a particular source.
Each source for an external interruption
has a subclass-mask bit assigned to it, and the source can cause an interruption
only when the external-mask bit is one
and the corresponding subclass-mask bit is one. The use of the subclass-mask
bits does not depend on whether the CPU is in the EC or BC mode.
When the CPU becomes enabled for a pend­
ing external-interruption condition, the
interruption occurs at the completion of
the instruction execution or inter­
ruption that causes the enabling.
More than one source may present a
request for an external interruption at
the same time. When the CPU becomes
enabled for more than one concurrently
pending request, the interruption occurs
for the pending condition or conditions
having the highest priority.
The priorities for external-interruption
requests in descending order are as
follows:
Interval timer, interrupt
external signals 2-7
Malfunction alert
key,