to storage; on an output operation, the difference is equal to the number of
bytes transferred to the I/O device.
The residual count, in conjunction with
the original count specified in the last CCW used, indicates the number of bytes
transferred to or from the area desig­
nated by the CCW. When an input opera­
tion is concluded, the difference
between the original count in the CCW and the residual count in the CSW is
equal to the number of bytes transferred The figure "Contents of the Count Field
in the CSW" lists the contents of the
count field for all situations that can
cause the CSW to be stored. They are listed in the order of priority; that
is, if two situations occur, the CSW appears as for the situation higher on
the list.
Situations I/O instruction issued when
channel logout-pending
Channel-control check
Status stored by START I/O or
START I/O FAST RELEASE
Status stored by HALT I/O or
HALT DEVICE Program check
Protection check Chaining check
Termination under count control
Termination by I/O device
Termination by HALT I/O or
HALT DEVICE Termination by CLEAR I/O Suppression of command
chaining due to unit check,
attention, or unit exception
with device end, channel end,
or control-unit end
Termination on command chaining by busy, attention, unit
check, or unit exception
Deferred condition code 1 or 3 PCI flag in CCW Interface-control check Channel end after HALT I/O or
HALT DEVICE on selector chan­
nel (and, depending on design
of the subchannel, on block­
multiplexer channel) Channel end after CLEAR I/O Control-unit end Device end Attention
Busy
Status modifier
Channel-available interruption Contents of Field
Zero
Unpredictable
Unchanged
Unchanged
Unpredictable
Unpredictable
Unpredictable Correct Correct Unpredictable
Unpredictable Correct. Residual count of last CCW used in the completed
operation. Correct. Original count of CCW specifying the new
operation.
Unpredictable
Unpredictable
Unpredictable
Zero
Zero
Zero Zero Zero Zero Zero Zero Contents of the Count Field in the CSW Chapter 13. Input/Output Operations 13-77

status
The status bits identify the situations
that have been detected during the I/O operation, that have caused a command to
be rejected, or that have been generated
by external events.
When the channel detects several errors,
all corresponding status bits in the CSW may be set to ones or only one may be
set, depending on the error and model.
Errors associated with equipment
malfunctioning have precedence, and
whenever malfunctioning causes an opera­
tion to be terminated, channel-control
check, interface-control check, or
channel-data check is indicated, depend­
ing on the error. When an operation is
concluded by program check, protection
check, or chaining check, the channel
identifies the situation responsible for
the conclusion and mayor may not indi­ cate incorrect length. When a data
error has been detected and the opera­
tion is concluded prematurely because of
a program check, protection check, or
chaining check, both channel-data check
and the other error are identified.
13-78 System/370 Principles of Operation
If the CCW fetched on command chaining
has the PCI flag set to one but a
programming error in the contents of the CCW precludes the initiation of the
operation, it is unpredictable whether
the PCI bit is one in the CSW associated
with the interruption condition.
However, if the CCW fetched on command
chaining has the PCI flag set to one but
an unusual situation detected by the
device precludes the initiation of the
operation, the PCI bit is one in the CSW associated with the interruption condi­
tion. Similarly, the PCI bit is
unpredictable in a CSW stored by START I/O or START I/O FAST RELEASE or in a CSW that has a nonzero deferred condi­
tion code.
Situations detected by the channel are
not related to those identified by the I/O device.
The figure "Contents of the CSW Status
Fields" summarizes the handling of
status bits. The figure lists the
states and activities that can cause
status indications to be created and the
methods by which these indications can
be placed in the CSW.