Mne- Op Name mon;c Character;st;cs Code CONNECT CHANNEL SET CONCS S C CS P $ B200 DIAGNOSE DM P DM 83 DISCONNECT CHANNEL SET DISCS S C CS P $ B201 EXTRACT PRIMARY ASN EPAR RRE DU Q SO R B226 EXTRACT SECONDARY ASN ESAR RRE DU Q SO R B227
INSERT ADDRESS SPACE CONTROL lAC RRE C DU Q SO R B224 INSERT PSW KEY IPK S PK Q G2 R B20B INSERT STORAGE KEY ISK RR P Al SP SO R 09 INSERT STORAGE KEY EXTENDED ISKE RRE EK P Al R B229 INSERT VIRTUAL STORAGE KEY IVSK RRE DU Q Al SO R B223
INVALIDATE PAGE TABLE ENTRY IPTE RRE EF P Al $ B221 LOAD ADDRESS SPACE PARAMETERS lASP SSE C DU P AS SP SO E500 LOAD CONTROL LCTL RS P A SP B7 LOAD PSW LPSW 5 L P A SP ¢ 82 LOAD REAL ADDRESS LRA RX C TR P Al R B1 MOVE TO PRIMARY MVCP SS C DU Q A SO ¢ ST DA MOVE TO SECONDARY MVCS SS C DU Q A SO ¢ ST DB MOVE WITH KEY MVCK SS C DU Q A ST D9 PROGRAM CALL PC S DU Q AT Zl T ¢ GM B R ST B218 PROGRAM TRANSFER PT RRE DU Q AT SP Z2 T ¢ B ST B228 PURGE TlB PTLB 5 TR P $ B20D READ DIRECT ROD 51 DC P Al $ SO 85
RESET REFERENCE BIT RRB S C TR P Al SO B213
RESET REFERENCE BIT EXTENDED RRBE RRE C EK P Al B22A
SET ADDRESS SPACE CONTROL SAC 5 DU SP SO ¢ B219
SET CLOCK SCK 5 C P A SP B204 SET CLOCK COMPARATOR SCKC S CK P A SP B206 SET CPU TIMER SPT S CK P A SP B208 SET PREFIX SPX 5 MP P A SP $ B210 SET PSW KEY FROM ADDRESS SPKA S PK Q B20A SET SECONDARY ASN SSAR RRE DU AT Z3 T ¢ ST B225
SET STORAGE KEY SSK RR P Al SP SO ¢ 08 SET STORAGE KEY EXTENDED SSKE RRE EK P Al ¢ B22B
SET SYSTEM MASK SSM S P A SP SO 80 SIGNAL PROCESSOR SIGP RS C MP P $ R AE STORE CLOCK COMPARATOR STCKC 5 CK P A SP ST B207 STORE CONTROL STCTl RS P A SP ST B6 STORE CPU ADDRESS STAP S MP P A SP ST B212 STORE CPU ID STIDP S P A SP ST B202 STORE CPU TIMER STPT S CK P A SP ST B209 STORE PREFIX STPX S MP P A SP ST B211 STORE THEN AND SYSTEM MASK STNSM SI TR P A ST AC STORE THEN OR SYSTEM MASK STOSM 51 TR P A SP ST AD
TEST BLOCK TB RRE C TB P Al II $ GO R B22C TEST PROTECTION TPROT SSE C EF P Al E501 WRITE DIRECT WRD SI DC P Al $ 84
Summary of Control Instruct;ons (Part 1 of 2) Chapter 10. Control Instructions 10-3

Explanation: ¢ Causes serialization and checkpoint synchronization.
$ Causes serialization.
A Access exceptions for logical addresses.
Al Access exceptions; not all access exceptions may occur; see instruc­
tion description for details.
AS Access exceptions and ASN-translation-specification exception; see
instruction description for details.
AT ASN-translation exceptions (which include addressing, ASN-translation
specification, AFX translation, and ASX translation).
B PER branch event. C Condition code is set. CK CPU-timer and clock-comparator facility. CS Channel-set-switching facility. DC Direct-control facility.
DM Depending on the model, DIAGNOSE may generate various program excep-
tions and may change the condition code.
DU Dual-address-space facility.
EF Extended facility.
EK Storage-key-instruction-extension facility. GO Instruction execution includes the implied use of general register O. G2 Instruction execution includes the implied use of general register 2.
GM Instruction execution includes the implied use of general registers
3, 4, and 14.
II Interruptible instruction.
L New condition code is loaded.
MP Multiprocessing facility.
P Privileged-operation exception.
PK PSW-key-handling facility.
Q Privileged-operation exception for semiprivileged instructions.
R PER general-register-alteration event.
RR RR instruction format.
RRE RRE instruction format. RS RS instruction format.
RX RX instruction format.
5 5 instruction format.
SD PER storage-alteration event, which can be caused by READ DIRECT only
when INVALIDATE PAGE TABLE ENTRY is not installed. 51 51 instruction format. SO Special-operation exception.
SP Specification exception. 55 SS instruction format. SSE SSE instruction format. ST PER storage-alteration event.
T Trace exceptions (which include access and specification).
TB Test-block facility.
TR Translation facility.
Zl Additional exceptions and events for PROGRAM CALL (which include
addressing, EX-translation, LX-translation, PC-translation-specifi­
cation, and special-operation exceptions and space-switch event). Z2 Additional exceptions and events for PROGRAM TRANSFER (which include
addressing, primary-authority, and special-operation exceptions and
space-switch event). Z3 Additional exceptions for SET SECONDARY ASN (which include addressing,
secondary authority, and special operation).
Summary of Control Instructions (Part 2 of 2) CONNECT CHANNEL SET
[5] 'B200' o 16 20 31
The channel set currently connected to
this CPU is disconnected, and the 10-4 System/370 Principles of Operation addressed channel set, if currently
disconnected, is connected to this CPU. The second-operand address, specified by
the B2 and D2 fields, is not used to
address data; bits 16-31 form the 16-bit
channel-set address. Bits 8-15 of the
second-operand address are ignored.
When the channel set currently connected
to this CPU is not the channel set
addressed by the instruction, the