The operation is nullified.
The instruction-length code is 2.
The lX-translation exception is indi­
cated by a program-interruption code of 0022 hex (or 00A2 hex if a concurrent PER event is indicated>.
Monitor Event
A monitor event is recognized when MONI­ TOR CAll is executed and the monitor­
mask bit in control register 8
corresponding to the class specified by
instruction bits 12-15 is one. The
information in control register 8 has
the following format: Control Register 8 I Monitor Masks I 16 31
The monitor-mask bits, bits 16-31 of
control register 8, correspond to moni­
tor classes 0-15, respectively. Any
number of monitor-mask bits may be on at a time; together they specify the class­
es of monitor events that are monitored at that time. The mask bits are initialized to zeros.
When MONITOR CALL is executed and the
corresponding monitor-mask bit is one, a program interruption for monitor event
occurs.
The monitor event can occur in both the EC and BC modes.
Additional information is stored at real
locations 148-149 and 156-159. The
format of the information stored at these locations is the same in the EC and BC modes and is as follows:
Real Locations 148-149
o 8
Monitor Class Ho. 15
Real Locations 156-159 1000000001 Monitor Code o 8 31
The contents of bit positions 8-15 of the MONITOR CALL instruction are stored
at real location 149 and constitute the
monitor-class number. Zeros are stored
at real location 148. The effective
address specified by the Bt and Dt
fields of the instruction forms the
monitor code, which is stored at real
locations 157-159. Zeros are stored at
real location 156.
The operation is completed.
The instruction-length code is 2.
The monitor event is indicated by a
program-interruption code of 0040 hex
(or OOCO hex if a concurrent PER event
is indicated>. Operation Exception
An operation exception is recognized
when the CPU attempts to execute an
instruction with an invalid operation
code. The operation code may be unas­
signed, or the instruction with that
operation code may not be installed on
the CPU. For the purpose of checking the opera­
tion code of an instruction, the opera­
tion code is defined as follows:
1. When the first eight bits of an
instruction have the value B2, A4,
A5, A6, E4, or E5 hex, or have the
value 9C hex and the suspend-and­
resume facility is installed, the
first 16 bits form the operation
code.
2. In all other cases, the first eight
bits alone form the operation code.
The operation is suppressed.
The instruction-length code is 1, 2, or
3.
The operation exception is indicated by a program-interruption code of 0001 hex
(or 0081 hex if a concurrent PER event
is indicated>. Programming Notes
1. Some models may offer instructions
not described in this publication,
such as those provided for assists
or as part of special or custom
features. Consequently, operation
codes not described in this publi­
cation do not necessarily cause an operation exception to be recog­
nized. Furthermore, these
instructions may cause modes of
operation to be set up or may otherwise alter the machine so as to affect the execution of subse­
quent instructions. To avoid
causing such an operation, an instruction with an operation code
not described in this publication Chapter 6. Interruptions 6-21

should be executed only when
specific function associated
the operation code is desired.
2. The operation code 00, with a two­
byte instruction format, currently
is not assigned. It is improbable
that this operation code will ever be assigned.
3. In the case of I/O instructions
with hex values 90, 9E, 9F, and, on
machines without the suspend-and­
resume facility, 9C, in bit posi­
tions 0-7, the value of bit 15 is
used to distinguish between two
instructions. Bits 8-14, however, are not checked for zeros, and these operation codes never cause
an operation exception to be recog­ nized. On machines with the
suspend-and-resume facility, all 16
bits are checked for op codes
beginning 9C hex.
To ensure that presently written
programs operate correctly if and when the I/O operation codes (90, 9E, and 9F) are extended further to
provide for new functions, only
zeros should be placed in the unas­ signed bit positions in the second
op-code byte. In accordance with these recommendations, the opera­
tion codes for the I/O instructions are shown as 9COO, 9COl, 9000, etc. Page-Translation Exception
A page-translation exception is recog­
nized when either:
1. The page-table entry indicated by
the page-index portion of a virtual
address is outside the page table.
2. The page-invalid bit is one. The exception is recognized as part of the execution of the instruction that needs the page-table entry in the trans­
lation of either an instruction or oper­
and address, except for the operand address in LOAD REAL ADDRESS and TEST PROTECTION, in which case the condition is indicated by the setting of the
condition code.
The segment-index and page-index portion
of the virtual address causing the
exception is stored at real locations
145-147. When DAS is installed, bit 0 of real location 144 is set to zero if the virtual address was relative to the
primary address space, or it is set to
one if the virtual address was relative
to the secondary address space. When DAS is not installed, bi t 0 of real
location 144 is set to zero. Bits 1-7
of real location 144 are set to zeros. When 2K-byte pages are used, the right-
6-22 System/370 Principles of Operation most 11 bits of the address stored are
unpredictable; when 4K-byte pages are
used, the rightmost 12 bits of the
address stored are unpredictable.
The unit of operation is nullified.
When the exception occurs during fetch­
ing of an instruction, it is unpredict­ able whether the ILC is 1, 2, or 3.
When the exception occurs during a reference to the target of EXECUTE, the ILC is 2.
When the exception occurs during a reference to an operand location, the instruction-length code (ILC) is 1, 2,
or 3 and indicates the length of the
instruction causing the exception.
The page-translation exception is indi­ cated by a program-interruption code of 0011 hex (or 0091 hex if a concurrent PER event is indicated). PC-Translation-Specification Exception
A PC-translation-specification exception
is recognized during PC-number trans­
lation in PROGRAM CALL when bit posi­
tions 1-7 of a valid linkage-table entry
do not contain zeros or when bit posi­
tions 32-39 of the entry-table entry are not all zeros.
The operation is suppressed. The instruction-length code is 2.
The PC-translation-specification tion is indicated by a
interruption code of OOIF hex
hex if a concurrent PER event
cated) .
A PER event is recognized when is enabled for PER and one or
these events occur.
excep­
program­
(or 009F is indi-
the CPU more of
The PER mask, bit 1 of the EC-mode PSW, controls whether the CPU is enabled for PER. PER is disallowed in the BC mode.
When the PER mask is zero, or in the BC
mode, PER events are not recognized.
When the bit is one, PER events are
recognized, subject to the PER-event­ mask bits in control register 9. The unit of operation is completed,
unless another condition has caused the
unit of operation to be inhibited, nullified, suppressed, or terminated.
Additional
event is 150-155.
information identifying the stored at real locations