in START I/O and START I/O FAST
RELEASE 1-2 in store accesses I-I in subchannel interruption-pending
state 1-2
completion
of I/O operations 13-54
of instruction execution 5-9
of unit of operation 5-10 conceptual sequence 5-24
as related to storage-operand
accesses 5-32
conclusion
of data transfer (I/O) 13-56
of I/O operations 13-54
of instruction execution 5-8 CONCS (CONNECT CHANNEL SET) instruction 10-4 concurrency of access for storage refer­
ences 5-31
condition code 4-7
deferred (See deferred condition
code)
for I/O operations 13-12
in BC-mode PSW 4-8
in EC-mode PSW 4-7
summary C-l tested by BRANCH ON CONDITION instruction 7-10 used for decision making 5-6
validity bit for 11-22
conditional-swapping facility 0-2
conditional swapping instructions (See COMPARE AND SWAP instruction, COMPARE DOUBLE AND SWAP instruction)
conditions for interruption (See inter­
ruption)
configuration 2-2
of storage 3-5 CONNECT CHANNEL SET (CONCS) instruction 10-4 connection of channels (See channel
set)
connective (See logical connective)
consistency (storage operand) 5-30 examples A-44,A-47
console device 12-1
control 4-2 as an I/O command 13-50 instructions 10-2 manual (See manual operation)
control register 2-4,4-8 save areas 3-45
validity bit 11-23
control-register assignment 4-10 (CRx.y indicates control register x,
bit position y) CRO.O: block-multiplexing-control bit
13-5,13-17,13-27 CRO.1: SSM-suppression-control bit 6-25,10-46 CRO.2: TOD-clock-sync-control bit
4-24,4-27 CRO.3: low-address-protection-control bit
3-9 CRO.4: extraction-authority-control bit
5-17 CRO.5: secondary-space-control bit
3-23,5-18 CRO.7: storage-key exception-control bit 3-7,6-26 CRO.8-12: translation format 3-23 CRO.14: vector-control bit 4-11 CRO.16: malfunction-alert subclass-mask bit 6-13 CRO.17: emergency-signal subclass-mask bit
6-11 CRO.18: external-call subclass-mask bit
6-12 CRO.19: TOO-clock sync-check subclass-mask bit 6-13 CRO.20: clock-comparator subclass-mask bit 6-11 CRO.21: CPU-timer subclass-mask bit 6-11 CRO.22: service-signal subclass-mask bit
6-13 CRO.24: interval-timer subclass-mask bit
6-12 CRO.25: interrupt-key subclass-mask bit 6-12 CRO.26: external-signal subclass-mask bit
6-12 CRl.0-7: primary segment-table length
(PSTL) 3-24 CR1.8-25: primary segment-table origin (PSTO) 3-24 CR1.31: space-switch-event-control bit
3-24,6-25 CR2.0-31: channel masks 6-14 CR3.0-15: PSW-key mask (PKM) 5-18 CR3.16-31: secondary ASN (SASN) 3-13,5-14 CR4.0-15: authorization index (AX)
3-17,5-18
CR4.16-31:
primary ASN (PASN) 3-13,5-14 CR5.0: subsystem-linkage-control bit
5-18,5-21 CR5.8-24: linkage-table origin (LTO) 5-21 CR5.25-31: linkage-table length (LTL) 5-21 CR7.0-7: secondary segment-table length
(SSTL) 3-24 CR7.8-25: secondary segment-table origin (SSTO) 3-24 CR8.16-31: monitor-mask bits 6-21 CR9.0: Index X-5

PER successful-branching-event­
mask bit 4-16 CR9.1: PER instruction-fetching-event­
mask bit 4-16 CR9.2: PER storage-alteration-event-mask
bit 4-16 CR9.3: PER general-register-alteration­
event-mask bit 4-16 CR9.16-31: PER general-register-mask bits
4-16 CR10.8-31: PER starting address 4-16 CR11.8-31: PER ending address 4-16 CR14.0: check-stop-control bit 11-28 CR14.1: synchronous machine-check
extended-logout-control bit
11-29 CR14.2: I/O extended-logout-control bit
11-29 CR14.4: recovery subclass-mask bit 11-28 CR14.5: degradation subclass-mask bit
11-28 CR14.6: external-damage subclass-mask bit
11-28 CR14.7: warning subclass-mask bit 11-28 CR14.8: asynchronous machine-check
extended-logout-control bit
11-29 CR14.9: asynchronous fixed-logout-control
bit 11-29 CR14.12: ASN-translation-control bit
3-13,5-18 CR14.20-31: ASN-first-table origin (AFTO)
3-13 CR15.8-28: machine-check extended-logout
address 11-29
control unit 2-6,13-3
sharing of 13-5
control unit busy (unit status) 13-29
control-unit end (unit status)
13-29,13-64
conversion
binary-to-decimal 7-17
example A-16
decimal-to-binary 7-16
example A-16
decimal-to-hexadecimal F-1
floating-point-number
basic example A-7
examples with instructions A-38
hexadecimal-to-decimal F-1
of hexadecimal and decimal fractions
F-7
of hexadecimal and decimal integers
F-6
X-6 System/370 Principles of Operation of program from BC to EC mode 10-46 CONVERT TO BINARY (CVB) instruction
7-16
example A-16 CONVERT TO DECIMAL (CVD) instruction
7-17
example A-16
count field
in CCW 13-38,13-40 in CSW 13-63,13-77
counter updating (example) A-41
counting operations 7-11 CP (COMPARE DECIMAL) instruction 8-5
example A-31 CPU (central processing unit) 2-3
address 4-38 assigned storage locations for 3-42
when stored during external inter-
ruptions 6-10 checkpoint 11-3
effect of power-on reset on 4-35
hangup due to string of interruptions
4-3
identification (10) 10-48 model number 10-48 registers 2-3
save areas for 3-44
reset 4-33
signal-processor order 4-39
retry 11-3
serialization 5-33
signaling 4-38
state 4-2
check-stop 4-3
load 4-3
no effect on TOO clock 4-24
operating 4-2
stopped 4-2
version code 10-48 CPU-identity field for DAS tracing
(assigned storage location) 3-45 CPU timer 4-28
as part of facility 0-2 external interruption 6-11
save areas for 3-44
validity bit for 11-23 CPU-timer and clock-comparator facility 0-2 CR (See control register) CR (COMPARE) binary instruction 7-12 CS (COMPARE AND SWAP) instruction 7-12
examples A-40 CSW (channel-status word)
assigned storage locations for 3-42
format of 13-62
information provided by 13-73 CCW address 13-75
count 13-77
deferred condition code 13-74
status 13-78
subchannel key 13-73
suspended indication 13-74
current PSW 4-3,5-6
(See also PSW) stored during interruption 6-2 CVB (CONVERT TO BINARY) instruction
7-16
example A-16 CVD (CONVERT TO DECIMAL) instruction
7-17
example A-16