GA22-7000-10 IBM System/370 Principles of Operation Sept 1987 Page X-5 (534 of 558)

in START I/O and START I/O FAST
RELEASE 1-2 in store accesses I-I in subchannel interruption-pending
state 1-2
completion
of I/O operations 13-54
of instruction execution 5-9
of unit of operation 5-10 conceptual sequence 5-24
as related to storage-operand
accesses 5-32
conclusion
of data transfer (I/O) 13-56
of I/O operations 13-54
of instruction execution 5-8 CONCS (CONNECT CHANNEL SET) instruction 10-4 concurrency of access for storage refer
ences 5-31
condition code 4-7
deferred (See deferred condition
code)
for I/O operations 13-12
in BC-mode PSW 4-8
in EC-mode PSW 4-7
summary C-l tested by BRANCH ON CONDITION instruction 7-10 used for decision making 5-6
validity bit for 11-22
conditional-swapping facility 0-2
conditional swapping instructions (See COMPARE AND SWAP instruction, COMPARE DOUBLE AND SWAP instruction)
conditions for interruption (See inter
ruption)
configuration 2-2
of storage 3-5 CONNECT CHANNEL SET (CONCS) instruction 10-4 connection of channels (See channel
set)
connective (See logical connective)
consistency (storage operand) 5-30 examples A-44,A-47
console device 12-1
control 4-2 as an I/O command 13-50 instructions 10-2 manual (See manual operation)
control register 2-4,4-8 save areas 3-45
validity bit 11-23
control-register assignment 4-10 (CRx.y indicates control register x,
bit position y) CRO.O: block-multiplexing-control bit
13-5,13-17,13-27 CRO.1: SSM-suppression-control bit 6-25,10-46 CRO.2: TOD-clock-sync-control bit
4-24,4-27 CRO.3: low-address-protection-control bit
3-9 CRO.4: extraction-authority-control bit
5-17 CRO.5: secondary-space-control bit
3-23,5-18 CRO.7: storage-key exception-control bit 3-7,6-26 CRO.8-12: translation format 3-23 CRO.14: vector-control bit 4-11 CRO.16: malfunction-alert subclass-mask bit 6-13 CRO.17: emergency-signal subclass-mask bit
6-11 CRO.18: external-call subclass-mask bit
6-12 CRO.19: TOO-clock sync-check subclass-mask bit 6-13 CRO.20: clock-comparator subclass-mask bit 6-11 CRO.21: CPU-timer subclass-mask bit 6-11 CRO.22: service-signal subclass-mask bit
6-13 CRO.24: interval-timer subclass-mask bit
6-12 CRO.25: interrupt-key subclass-mask bit 6-12 CRO.26: external-signal subclass-mask bit
6-12 CRl.0-7: primary segment-table length
(PSTL) 3-24 CR1.8-25: primary segment-table origin (PSTO) 3-24 CR1.31: space-switch-event-control bit
3-24,6-25 CR2.0-31: channel masks 6-14 CR3.0-15: PSW-key mask (PKM) 5-18 CR3.16-31: secondary ASN (SASN) 3-13,5-14 CR4.0-15: authorization index (AX)
3-17,5-18
CR4.16-31:
primary ASN (PASN) 3-13,5-14 CR5.0: subsystem-linkage-control bit
5-18,5-21 CR5.8-24: linkage-table origin (LTO) 5-21 CR5.25-31: linkage-table length (LTL) 5-21 CR7.0-7: secondary segment-table length
(SSTL) 3-24 CR7.8-25: secondary segment-table origin (SSTO) 3-24 CR8.16-31: monitor-mask bits 6-21 CR9.0: Index X-5

PER successful-branching-event
mask bit 4-16 CR9.1: PER instruction-fetching-event
mask bit 4-16 CR9.2: PER storage-alteration-event-mask
bit 4-16 CR9.3: PER general-register-alteration
event-mask bit 4-16 CR9.16-31: PER general-register-mask bits
4-16 CR10.8-31: PER starting address 4-16 CR11.8-31: PER ending address 4-16 CR14.0: check-stop-control bit 11-28 CR14.1: synchronous machine-check
extended-logout-control bit
11-29 CR14.2: I/O extended-logout-control bit
11-29 CR14.4: recovery subclass-mask bit 11-28 CR14.5: degradation subclass-mask bit
11-28 CR14.6: external-damage subclass-mask bit
11-28 CR14.7: warning subclass-mask bit 11-28 CR14.8: asynchronous machine-check
extended-logout-control bit
11-29 CR14.9: asynchronous fixed-logout-control
bit 11-29 CR14.12: ASN-translation-control bit
3-13,5-18 CR14.20-31: ASN-first-table origin (AFTO)
3-13 CR15.8-28: machine-check extended-logout
address 11-29
control unit 2-6,13-3
sharing of 13-5
control unit busy (unit status) 13-29
control-unit end (unit status)
13-29,13-64
conversion
binary-to-decimal 7-17
example A-16
decimal-to-binary 7-16
example A-16
decimal-to-hexadecimal F-1
floating-point-number
basic example A-7
examples with instructions A-38
hexadecimal-to-decimal F-1
of hexadecimal and decimal fractions
F-7
of hexadecimal and decimal integers
F-6
X-6 System/370 Principles of Operation of program from BC to EC mode 10-46 CONVERT TO BINARY (CVB) instruction
7-16
example A-16 CONVERT TO DECIMAL (CVD) instruction
7-17
example A-16
count field
in CCW 13-38,13-40 in CSW 13-63,13-77
counter updating (example) A-41
counting operations 7-11 CP (COMPARE DECIMAL) instruction 8-5
example A-31 CPU (central processing unit) 2-3
address 4-38 assigned storage locations for 3-42
when stored during external inter-
ruptions 6-10 checkpoint 11-3
effect of power-on reset on 4-35
hangup due to string of interruptions
4-3
identification (10) 10-48 model number 10-48 registers 2-3
save areas for 3-44
reset 4-33
signal-processor order 4-39
retry 11-3
serialization 5-33
signaling 4-38
state 4-2
check-stop 4-3
load 4-3
no effect on TOO clock 4-24
operating 4-2
stopped 4-2
version code 10-48 CPU-identity field for DAS tracing
(assigned storage location) 3-45 CPU timer 4-28
as part of facility 0-2 external interruption 6-11
save areas for 3-44
validity bit for 11-23 CPU-timer and clock-comparator facility 0-2 CR (See control register) CR (COMPARE) binary instruction 7-12 CS (COMPARE AND SWAP) instruction 7-12
examples A-40 CSW (channel-status word)
assigned storage locations for 3-42
format of 13-62
information provided by 13-73 CCW address 13-75
count 13-77
deferred condition code 13-74
status 13-78
subchannel key 13-73
suspended indication 13-74
current PSW 4-3,5-6
(See also PSW) stored during interruption 6-2 CVB (CONVERT TO BINARY) instruction
7-16
example A-16 CVD (CONVERT TO DECIMAL) instruction
7-17
example A-16

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Extracted Text (may have errors)

in START I/O and START I/O FAST
RELEASE 1-2 in store accesses I-I in subchannel interruption-pending
state 1-2
completion
of I/O operations 13-54
of instruction execution 5-9
of unit of operation 5-10 conceptual sequence 5-24
as related to storage-operand
accesses 5-32
conclusion
of data transfer (I/O) 13-56
of I/O operations 13-54
of instruction execution 5-8 CONCS (CONNECT CHANNEL SET) instruction 10-4 concurrency of access for storage refer
ences 5-31
condition code 4-7
deferred (See deferred condition
code)
for I/O operations 13-12
in BC-mode PSW 4-8
in EC-mode PSW 4-7
summary C-l tested by BRANCH ON CONDITION instruction 7-10 used for decision making 5-6
validity bit for 11-22
conditional-swapping facility 0-2
conditional swapping instructions (See COMPARE AND SWAP instruction, COMPARE DOUBLE AND SWAP instruction)
conditions for interruption (See inter
ruption)
configuration 2-2
of storage 3-5 CONNECT CHANNEL SET (CONCS) instruction 10-4 connection of channels (See channel
set)
connective (See logical connective)
consistency (storage operand) 5-30 examples A-44,A-47
console device 12-1
control 4-2 as an I/O command 13-50 instructions 10-2 manual (See manual operation)
control register 2-4,4-8 save areas 3-45
validity bit 11-23
control-register assignment 4-10 (CRx.y indicates control register x,
bit position y) CRO.O: block-multiplexing-control bit
13-5,13-17,13-27 CRO.1: SSM-suppression-control bit 6-25,10-46 CRO.2: TOD-clock-sync-control bit
4-24,4-27 CRO.3: low-address-protection-control bit
3-9 CRO.4: extraction-authority-control bit
5-17 CRO.5: secondary-space-control bit
3-23,5-18 CRO.7: storage-key exception-control bit 3-7,6-26 CRO.8-12: translation format 3-23 CRO.14: vector-control bit 4-11 CRO.16: malfunction-alert subclass-mask bit 6-13 CRO.17: emergency-signal subclass-mask bit
6-11 CRO.18: external-call subclass-mask bit
6-12 CRO.19: TOO-clock sync-check subclass-mask bit 6-13 CRO.20: clock-comparator subclass-mask bit 6-11 CRO.21: CPU-timer subclass-mask bit 6-11 CRO.22: service-signal subclass-mask bit
6-13 CRO.24: interval-timer subclass-mask bit
6-12 CRO.25: interrupt-key subclass-mask bit 6-12 CRO.26: external-signal subclass-mask bit
6-12 CRl.0-7: primary segment-table length
(PSTL) 3-24 CR1.8-25: primary segment-table origin (PSTO) 3-24 CR1.31: space-switch-event-control bit
3-24,6-25 CR2.0-31: channel masks 6-14 CR3.0-15: PSW-key mask (PKM) 5-18 CR3.16-31: secondary ASN (SASN) 3-13,5-14 CR4.0-15: authorization index (AX)
3-17,5-18
CR4.16-31:
primary ASN (PASN) 3-13,5-14 CR5.0: subsystem-linkage-control bit
5-18,5-21 CR5.8-24: linkage-table origin (LTO) 5-21 CR5.25-31: linkage-table length (LTL) 5-21 CR7.0-7: secondary segment-table length
(SSTL) 3-24 CR7.8-25: secondary segment-table origin (SSTO) 3-24 CR8.16-31: monitor-mask bits 6-21 CR9.0: Index X-5

PER successful-branching-event
mask bit 4-16 CR9.1: PER instruction-fetching-event
mask bit 4-16 CR9.2: PER storage-alteration-event-mask
bit 4-16 CR9.3: PER general-register-alteration
event-mask bit 4-16 CR9.16-31: PER general-register-mask bits
4-16 CR10.8-31: PER starting address 4-16 CR11.8-31: PER ending address 4-16 CR14.0: check-stop-control bit 11-28 CR14.1: synchronous machine-check
extended-logout-control bit
11-29 CR14.2: I/O extended-logout-control bit
11-29 CR14.4: recovery subclass-mask bit 11-28 CR14.5: degradation subclass-mask bit
11-28 CR14.6: external-damage subclass-mask bit
11-28 CR14.7: warning subclass-mask bit 11-28 CR14.8: asynchronous machine-check
extended-logout-control bit
11-29 CR14.9: asynchronous fixed-logout-control
bit 11-29 CR14.12: ASN-translation-control bit
3-13,5-18 CR14.20-31: ASN-first-table origin (AFTO)
3-13 CR15.8-28: machine-check extended-logout
address 11-29
control unit 2-6,13-3
sharing of 13-5
control unit busy (unit status) 13-29
control-unit end (unit status)
13-29,13-64
conversion
binary-to-decimal 7-17
example A-16
decimal-to-binary 7-16
example A-16
decimal-to-hexadecimal F-1
floating-point-number
basic example A-7
examples with instructions A-38
hexadecimal-to-decimal F-1
of hexadecimal and decimal fractions
F-7
of hexadecimal and decimal integers
F-6
X-6 System/370 Principles of Operation of program from BC to EC mode 10-46 CONVERT TO BINARY (CVB) instruction
7-16
example A-16 CONVERT TO DECIMAL (CVD) instruction
7-17
example A-16
count field
in CCW 13-38,13-40 in CSW 13-63,13-77
counter updating (example) A-41
counting operations 7-11 CP (COMPARE DECIMAL) instruction 8-5
example A-31 CPU (central processing unit) 2-3
address 4-38 assigned storage locations for 3-42
when stored during external inter-
ruptions 6-10 checkpoint 11-3
effect of power-on reset on 4-35
hangup due to string of interruptions
4-3
identification (10) 10-48 model number 10-48 registers 2-3
save areas for 3-44
reset 4-33
signal-processor order 4-39
retry 11-3
serialization 5-33
signaling 4-38
state 4-2
check-stop 4-3
load 4-3
no effect on TOO clock 4-24
operating 4-2
stopped 4-2
version code 10-48 CPU-identity field for DAS tracing
(assigned storage location) 3-45 CPU timer 4-28
as part of facility 0-2 external interruption 6-11
save areas for 3-44
validity bit for 11-23 CPU-timer and clock-comparator facility 0-2 CR (See control register) CR (COMPARE) binary instruction 7-12 CS (COMPARE AND SWAP) instruction 7-12
examples A-40 CSW (channel-status word)
assigned storage locations for 3-42
format of 13-62
information provided by 13-73 CCW address 13-75
count 13-77
deferred condition code 13-74
status 13-78
subchannel key 13-73
suspended indication 13-74
current PSW 4-3,5-6
(See also PSW) stored during interruption 6-2 CVB (CONVERT TO BINARY) instruction
7-16
example A-16 CVD (CONVERT TO DECIMAL) instruction
7-17
example A-16

Help

byte-multiplexer channel 13-4,13-30 byte-oriented-operand facility 3-5
C
C (COMPARE) binary instruction 7-12
cache 3-2
CAr (channel-available interruption)
13-29,13-61
carry 7-3
CAW (channel-address word) 13-37
assigned storage locations for 3-42
in IPl 4-36
CBC (checking-block code) 11-2
invalid 11-2
in registers 11-9
in storage 11-6
in storage keys 11-7
near-valid 11-2
valid 11-2
CC (chain-command) flag in CCW
13-7,13-38
CCW (channel-command word) 13-38
address of in CAW 13-37
address of in CSW 13-63
contents of 13-75
validity flag for 13-82
chaining of 13-40 commands (See command chaining of
cews)
data (See data chaining of CCWs)
command codes (See commands)
command retry of 13-53
count field in (See count field)
data-address field in 13-39
flags in 13-49
format of 13-38
in rPl 4-36
assigned storage locations for
3-41
prefetching of 13-40,13-42 role of in I/O operations 13-5
CD (chain-data) flag in CCW 13-6,13-38
CD (COMPARE) floating-point instruction
9-8
CDR (COMPARE) floating-point instruction
9-8
examples A-37
CDS (COMPARE DOUBLE AND SWAP) instruc
tion 7-12
examples A-40 CE (COMPARE) floating-point instruction
9-8
central processing unit (See CPU) CER (COMPARE) floating-point instruction
9-8
CH (COMPARE HAlFWORD) instruction 7-14
example A-12
chain-command (CC) flag in CCW
13-7,13-38
chain-data (CD) flag in cew 13-6,13-38
chaining 13-40 command (See command chaining of
CCWs)
data (See data chaining of CCWs)
flags in CCW for 13-6,13-38
chaining check (channel status) 13-72
change bit in storage key 3-7
change recording 3-10 channel 2-6,13-3
block-multiplexer 13-5
byte-multiplexer 13-4,13-30 control failure (bit in
external-damage code) 11-25
equipment error detected by 13-14
I/O-system reset, as part of subsys
tem reset 4-34
masks 6-14
difference between EC and BC modes
4-4
in BC-mode PSW 4-8
multiplexer 13-5
not operational (I/O-system state)
13-12
bit in external-damage code 11-25
programming error dptected by 13-14
selector 13-4
timeout used by 13-4
working (I/O-system state) 13-11
channel address 13-8,13-15
channel-address word (See CAW)
channel-available interruption (CAl)
13-29,13-61
channel-command word (See CeW)
channel commands (See commands)
channel-control check (channel status)
13-72
channel-data check (channel status)
13-71
channel end (unit status) 13-67
channel identification (rD) 13-32
assigned storage locations for 3-44
in IOeA (I/O-communication area) 13-80 channel indirect data addressing 13-45
facility D-2
IDA flag used for 13-38
role of in I/O operations 13-6
channel logout (See full channel
logout)
(See also limited channel logout)
channel model 13-32
channel power-on reset 4-35
channel program 13-5
resumption of 13-55
serialization 5-34
suspension of 13-46
channel set 2-6
address 4-43
resetting of connections for 4-34
switching 4-43
switching facility D-2
channel status 13-70 chaining check 13-72
channel-control check 13-72
channel-data check 13-71
incorrect length 13-70 interface-control check 13-72
program check 13-70 program-controlled interruption (PCI) 13-70 protection check 13-71
channel-status word (See CSW)
channel-to-channel adapter 13-2
publication referenced v
channel-type code (specified by STIDC)
13-32
characteristic (of floating-point
number) 9-1
characters, represented by eight-bit
code iv
check bits 3-3,11-2
check stop 4-3,11-10 as signal-processor status 4-42
control bit 11-14,11-28
during manual operation 12-1
Index X-3

effect on CPU timer 4-28
entering of 11-14
indicator 12-2
malfunction alert for 6-12
system 11-11
checking block 11-2
checking-block code (See CaC) checkpoint 11-3
in tracing 4-13
checkpoint synchronization 11-3
action 11-4
operations 11-4 CL (COMPARE LOGICAL) instruction 7-14 CLC (COMPARE LOGICAL) instruction 7-14 example A-13 CLCL (COMPARE LOGICAL LONG) instruction
7-15
example A-14 CLEAR CHANNEL (CLRCH) instruction 13-16
termination of I/O operation by
13-59 CLEAR I/O (CLRIO) instruction 13-17
termination of I/O operation by
13-59 clear-I/O facility D-2
clear reset 4-34
clearing operation
by clear-reset function 4-34
by load-clear key 12-3
by system-reset-clear key 12-5
by TEST BLOCK instruction 10-50 eLI (COMPARE LOGICAL) instruction 7-14 example A-13 CLM (COMPARE LOGICAL CHARACTERS UNDER
MASK) instruction 7-15
example A-14
clock (See TOD clock)
clock comparator 4-27
as part of facility 0-2 external interruption 6-11
save areas for 3-44
validity bit for 11-23
clock unit 4-26 CLR (COMPARE LOGICAL) instruction 7-14
example A-14 CLRCH (CLEAR CHANNEL) instruction 13-16 CLRIO (CLEAR I/O) instruction 13-17
code ASCII, handled by architecture iv
channel-type 13-32
checking-block (See CBC) command (See commands)
condition (See condition code)
decimal digit and sign 8-2 EBCDIC chart for G-l
handled by architecture iv
eight-bit, handled by architecture
i v
exception-extension 6-15
external-damage 11-24
validity bit for 11~22 instruction-length (See ILC) interruption (See interruption code)
monitor (See monitor code)
operation 5-2 PER (See PER code)
region 11-26
validity bit for 11-22
sequence (in limited channel logout)
13-82
version 10-48 command chaining of CCWs 13-43
X-4 System/370 Principles of Operation chain-command (CC) flag for in CCW 13-7,13-38
during IPL 4-36
command code in CCW (See commands)
command-retry facility D-2,13-53
commands (I/O) 13-48
basic sense 13-51
chaining of 13-43
code in CCW for 13-39
control 13-50 no-operation 13-50 read 13-49
read backward 13-50 rejection of 13-51,13-55
retry of 13-53
sense 13-51
sense ID 13-52
transfer in channel 13-53
write 13-49
commercial instruction set D-l
common-segment bit 3-25
communication area, I/O (See IOCA) COMPARE (C,CR) binary instructions 7-12 COMPARE (CD,CDR,CE,CER) floating-point
instructions 9-8 examples A-37 COMPARE AND SWAP (CS) instruction 7-12
examples A-40 COMPARE DECIMAL (CP) instruction 8-5 example A-31 COMPARE DOUBLE AND SWAP (CDS) instruc
t;on 7-12
examples A-40 COMPARE HALFWORD (CH) instruction 7-14
example A-12 COMPARE LOGICAL (CL,CLC,CLI,CLR) instructions 7-14
examples A-13 COMPARE LOGICAL CHARACTERS UNDER MASK (CLM) instruction 7-15
example A-14 COMPARE LOGICAL LONG (CLCL) instruction
7-15
example A-14
comparison
address (See address comparison)
decimal 8-5
example A-31
floating-point 9-8
examples A-37
logical 7-4
examples A-13
signed-binary 7-4 TOO-clock 4-27
compatibility 1-3
among systems in the same architec
tural mode 1-3
of BC-mode PSW with System/360 4-5
of I/O operations 13-7
compatibility differences
between System/360 and System/370 in channel prefetching H-2
in command retry H-2
in I/O operation codes H-l
in logout H-2
in USASCII-8 mode H-1
in validity of data H-2
within System/370 in change bit 1-2 in fetch accesses I-I in operand-access consistency 1-2
in REAL DIRECT and WRITE DIRECT I-I

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D
D (DIVIDE) binary instruction 7-17 example A-16
D field of instruction 5-5 damage code (external) 11-24
validity bit for 11-22 external 11-18
mask bit for 11-28
instruction-processing 11-17
interval-timer 11-17
processing 11-20
service-processor 11-18
system 11-16
timing-facility 11-17
DAS (dual-address-space) facility
D-2,5-13
authorization mechanisms 5-17
summary of 5-20 tracing (See tracing)
DAT (See dynamic address translation)
DAT mode (bit in PSW) 4-6 use in address translation 3-22
data
format for
decimal instructions 8-1
floating-point instructions 9-2 general instructions 7-2 I/O-sense 13-51
prefetching of for output operation 13-40 transfer (I/O), conclusion of 13-56
data block (See block of I/O data)
data chaining of CCWs 13-6,13-42
as cause of chaining check 13-72 CCW prefetch for 13-42
chain-data (CD) flag in CCW 13-6,13-38
effect on compatibility of 13-8
data check (bit in I/O-sense data)
13-51
data exception 6-18
DD (DIVIDE) floating-point instruction
9-9
DDR (DIVIDE) floating-point instruction
9-9
DE (DIVIDE) floating-point instruction
9-9
decimal
arithmetic 8-2
comparison 8-5
digit codes 8-2
divide exception 6-19
instructions 8-1 examples A-30 number representation 8-1 examples A-5
operand overlap 8-3
overflow
exception 6-19
mask in BC-mode PSW 4-8
mask in EC-mode PSW 4-7
sign codes 8-2
tables for conversion to hexadecimal
F-1
decimal-to-binary conversion 7-16
example A-16
deferred condition code (in CSW) 13-63
contents of 13-74
for SIOF function 13-29
degradation (machine-check condition)
11-18
subclass-mask bit for 11-28
degradation, storage (machine-check
condition) 11-21
delay code in I/O-communication area
13-83
delay in storing 5-29
delayed (machine-check condition) 11-19
delayed access exception (machine-check
condition) 11-19
deletion of malfunctioning unit 11-4
DER (DIVIDE) floating-point instruction
9-9
examples A-37
designation
authority-table 3-14
effective segment-table 3-27
entry-table 5-21
linkage-table 5-21
in AST entry 3-15
page-table 3-25
primary segment-table 3-24
secondary segment-table 3-24
segment-table 3-24
in AST entry 3-14
destructive overlap 5-32,7-25
detect field (in limited channel logout)
13-81 device 2-6,13-2
console 12-1
not-ready state of 13-10 status of 13-51
used for IPL 4-36
device address 13-8,13-15 device busy (unit status) 13-29
device end (unit status) 13-29,13-67
device error 13-15
device-working state (I/O-system state) 13-10 DIAGNOSE instruction 10-5 digit codes (decimal) 8-2
digit selector (in EDIT) 8-7
direct-access storage 3-2
direct control 4-23
facility D-2
disabling for interruptions 6-6
disabling of interval timer 4-29
disallowed interruptions 6-6 DISCONNECT CHANNEL SET (DISCS) instruc-
tion 10-6 DISCS (DISCONNECT CHANNEL SET) instruc
tion 10-6 displacement (in relative addressing)
5-5
display (manual controls) 12-2
DIVIDE (D,DR) binary instructions 7-17
example A-16
DIVIDE (DD,DDR,DE,DER) floating-point
instructions 9-9
examples A-37
DIVIDE DECIMAL (DP) instruction 8-5
example A-31
divide exception
decimal 6-19
fixed-point 6-20 floating-point 6-20 divisible instruction execution 5-25
doubleword 3-3
doubleword-concurrent storage references
5-31
DP (DIVIDE DECIMAL) instruction 8-5
example A-31
DR (DIVIDE) binary instruction 7-17
dual-address-space facility (See DAS)
dump (standalone) 12-5
dynamic address translation (DAT) 3-20 Index X-7

E
by LOAD REAL ADDRESS instruction 10-21 control of 3-22
explicit and implicit 3-27
mode bit in PSW 4-6
use in address translation 3-22
sequence of table fetches 5-27
early exception recognition 6-9
EBCDIC (Extended Binary-Coded-Decimal
Interchange Code)
architecture designed for iv character code, chart for G-1
EC (extended-control) mode 4-4
control bit in PSW 4-6,4-8 PSW format in 4-6
ECC (error checking and correction)
11-2
ED (EDIT) instruction 8-6
examples A-31
EDIT (ED) instruction 8-6
examples A-31
EDIT AND MARK (EDMK) instruction 8-9
example A-33
editing instructions 8-3
(See also ED instruction, EDMK
instruction)
EDMK (EDIT AND MARK) instruction 8-9
example A-33
effective address 3-6
used for storage interlocks 5-25
effective segment-table designation
3-27
EKM (entry key mask) 5-22
emergency signal (external interruption)
6-11
signal-processor order 4-39
enabling for interruptions 6-6
ending of I/O operations 13-54
ending of instruction execution 5-8
entry in trace table 4-14
entry index (EX) 5-21
entry key mask (EKM) 5-22
entry table (ET) 5-22
designation 5-21 EPAR (EXTRACT PRIMARY ASN) instruction 10-6 epoch (for TOO clock) 4-25
equipment check
bit in I/O-sense data 13-51
in signal-processor status 4-41
error
alert (in limited channel logout)
13-82
channel-equipment 13-14
channel-programming 13-14
checking and correction 11-2
device 13-15
from DIAGNOSE instruction 10-5 indirect storage 11-21
intermittent 11-5 PSW-format 6-9
solid 11-5
state of TOO clock 4-25
storage 11-20 storage-key 11-21
ESAR (EXTRACT SECONDARY ASH) instruction 10-7 ET (entry table) 5-22
ETL (entry-table length) 5-21
ETO (entry-table origin) 5-21
X-8 System/370 Principles of Operation
event 6-14
monitor 7-23
PER 4-15
space-switch 6-25
EX (entry index) 5-21
translation exception 6-20 EX (EXECUTE) (See EXECUTE instruction)
exception-extension code 6-15
exceptions 6-14
access (collective
program-interruption name)
6-28,6-33
addressing 6-15
AFX-translation 6-18
ASN-translation (collective
program-interruption name) 6-35
ASN-translation-specification 6-18
ASX-translation 6-18
data (decimal) 6-18
decimal-divide 6-19
decimal-overflow 6-19
delayed access (machine-check condi-
tion) 11-19
during translation 3-31
EX-translation 6-20 execute 6-19
exponent-overflow 6-19
exponent-underflow 6-19
fixed-point-divide 6-20 fixed-poi nt-overflow 6-20 floating-point-divide 6-20 LX-translation 6-20 operation 6-21
page-translation 6-22
PC-translation-specification 6-22
primary-authority 6-23
privileged-operation 6-23
for I/O instructions 13-36
protection 6-23 PSW-related 6-9
recognition of, early and late 6-9
secondary-authority 6-24
segment-translation 6-24
significance 6-25
special-operation 6-25
specification 6-26
trace (collective
program-interruption name) 6-35
translation-specification 6-27
unnormalized-operand 6-27
vector-operation 6-28
EXCLUSIVE OR (X,XC,XI,XR) instructions
7-18
examples A-17
EXECUTE (EX) instruction 7-19
effect of address comparison on 12-1
example A-18
exceptions while fetching target 6-8 PER event for target of 4-19
execute exception 6-19
exigent machine-check conditions 11-11
explicit address translation 3-27
exponent 9-1
(See also floating point)
overflow 9-1
exception 6-19
underflow 9-1
exception 6-19
mask in BC-mode PSW 4-8
mask in EC-mode PSW 4-7
extended control (See EC mode)
extended facility D-3
extended floating-point number 9-2
extended logout

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