GA22-7000-10 IBM System/370 Principles of Operation Sept 1987 Page C-1 (504 of 558)

This appendix lists the condition-code
setting for instructions in the System/370 architecture which set the
condition code. In addition to those
instructions listed which set the condi
tion code, the condition code may be
changed by DIAGNOSE and the target of EXECUTE. The condition code is loaded
by LOAD PSW, by SET PROGRAM MASK, and by
an interruption. The condition code is
set to zero by initial CPU reset and is
loaded by the successful conclusion of
the initial-program-loading sequence.
Instruction
ADD, ADD HALFWORD ADD DECIMAL
ADD LOGICAL ADD NORMALIZED
ADD UNNORMALIZED AND
CLEAR CHANNEL
CLEAR I/O COMPARE (gen, fl pt) COMPARE HALFWORD COMPARE AND SWAP COMPARE DECIMAL COMPARE DOUBLE AND SWAP COMPARE LOGICAL COMPARE LOGICAL CHARACTERS UNDER MASK COMPARE LOGICAL LONG CONNECT CHANNEL SET DISCONNECT CHANNEL SET
EDIT, EDIT AND MARK EXCLUSIVE OR HALT DEVICE HALT I/O INSERT ADDRESS SPACE CONTROL INSERT CHARACTERS UNDER MASK LOAD ADDRESS SPACE PARAMETERS LOAD AND TEST (gen, fl pt) LOAD COMPLEMENT (gen) LOAD COMPLEMENT (fl pt) LOAD NEGATIVE (gen, fl pt) LOAD POSITIVE (gen) LOAD POSITIVE (fl pt) LOAD REAL ADDRESS MOVE LONG MOVE TO PRIMARY, MOVE TO SECONDARY MOVE WITH KEY Zero
Zero
Zero,
o
no carry
Zero
Zero
Zero
Reset signaled
No operation
in progress
Equal
Equal
Equal
Equal
Equal
Equal
Equal
Equal
Successful
Successful
Zero
Zero
Interruption
pending/busy
Interruption
pending
Zero
All zeros Parameters loaded
Zero
Zero
Zero
Zero
Zero
Zero
Translation
available
Length equal
Length =< 256
Length =< 256
APPENDIX ~ CONDITION-CODE SETTINGS
The condition codes for the vector
facility are not included in this appen
dix. See the pUblication IBM System/370 Vector Operations, SA22-7125, for the
condition codes set by vector
instructions.
Some models may offer instructions which
set the condition code and do not appear
in this document, such as those provided
for assists or as part of special or
custom features.
Condition Code
1
< zero
< zero
Not zero,
no carry
< zero
< zero
Not zero CSW stored
Low
Low
Not equal
Low
Not equal
Low
Low
Low
Connected to
another CPU Connected to
another CPU < zero
Not zero CSW stored
CSW stored One First bit one Primary ASN not available
< zero
< zero
< zero
< zero
ST entry
invalid
Length low
> zero
> zero
Zero,
carry
> zero
> zero
2
Channel busy
Channel busy
High
High
High
High
High
High
> zero
3 Overflow Overflow Not zero,
carry
Not operational
Not operational
Not operational
Not operational Channel Not operational
working
Burst operation Not operational
terminated
First bit zero --
Secondary ASN Space-switch
not available event
or not
authorized
> zero
> zero
> zero
> zero
> zero PT entry
invalid
Length high Overflow Overflow Length
violation
Destructive
overlap
length > 256
Length > 256
Summary of Condition-Code Settings (Part 1 of 2)
Appendix C. Condition-Code Settings C-l

Condition Code
Instruction 0 1 2 3 OR Zero Not zero -- --
RESET REFERENCE BIT, RESET R bit zero, R bit zero, R bit one, R bit one,
REFERENCE BIT EXTENDED C bit zero C bit one C bit zero C bit one
RESUME I/O Successful ----Not operational
SET CLOCK Set Secure --Not operational
SHIFT AND ROUND DECIMAL Zero < zero > zero Overflow SHIFT LEFT (DOUBLE/SINGLE) Zero < zero > zero Overflow
SHIFT RIGHT (DOUBLE/SINGLE) Zero < zero > zero --
SIGNAL PROCESSOR Order accepted Status stored Busy Not operational
START I/O, START I/O FAST Successful CSW stored Busy Not operational
,RELEASE STORE CHANNEL ID ID stored CSW stored Busy Not operational STORE CLOCK Set Not set Error Not operational
SUBTRACT, SUBTRACT HALFWORD Zero < zero > zero Overflow
SUBTRACT DECIMAL Zero < zero > zero Overflow
SUBTRACT LOGICAL --Not zero, Zero, Not zero,
no carry carry carry
SUBTRACT NORMALIZED Zero < zero > zero --
SUBTRACT UNNORMALIZED Zero < zero > zero --
TEST AND SET Left bit zero Left bit one ----
TEST BLOCK Usable Not usable ----
TEST CHANNEL Available Interruption Burst mode Not operational
pending
TEST I/O Available CSW stored Busy Not operational
TEST PROTECTION Can fetch, Can fetch, Cannot fetch, Translation not
can store cannot store cannot store available
TEST UNDER MASK All zeros Mixed --All ones
TRANSLATE AND TEST All zeros Incomplete Complete -- ZERO AND ADD Zero < zero > zero Overflow
EXElanation:
-- Not applicable
> zero Result greater than zero
< zero Result less than zero
=< 256 Equal to, or less than, 256
> 256 Greater than 256
High First operand high
Low First operand low
length Length of first operand
Summary of Condition-Code Settings (Part 2 of 2)
C-2 System/370 Principles of Operation

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Extracted Text (may have errors)

This appendix lists the condition-code
setting for instructions in the System/370 architecture which set the
condition code. In addition to those
instructions listed which set the condi
tion code, the condition code may be
changed by DIAGNOSE and the target of EXECUTE. The condition code is loaded
by LOAD PSW, by SET PROGRAM MASK, and by
an interruption. The condition code is
set to zero by initial CPU reset and is
loaded by the successful conclusion of
the initial-program-loading sequence.
Instruction
ADD, ADD HALFWORD ADD DECIMAL
ADD LOGICAL ADD NORMALIZED
ADD UNNORMALIZED AND
CLEAR CHANNEL
CLEAR I/O COMPARE (gen, fl pt) COMPARE HALFWORD COMPARE AND SWAP COMPARE DECIMAL COMPARE DOUBLE AND SWAP COMPARE LOGICAL COMPARE LOGICAL CHARACTERS UNDER MASK COMPARE LOGICAL LONG CONNECT CHANNEL SET DISCONNECT CHANNEL SET
EDIT, EDIT AND MARK EXCLUSIVE OR HALT DEVICE HALT I/O INSERT ADDRESS SPACE CONTROL INSERT CHARACTERS UNDER MASK LOAD ADDRESS SPACE PARAMETERS LOAD AND TEST (gen, fl pt) LOAD COMPLEMENT (gen) LOAD COMPLEMENT (fl pt) LOAD NEGATIVE (gen, fl pt) LOAD POSITIVE (gen) LOAD POSITIVE (fl pt) LOAD REAL ADDRESS MOVE LONG MOVE TO PRIMARY, MOVE TO SECONDARY MOVE WITH KEY Zero
Zero
Zero,
o
no carry
Zero
Zero
Zero
Reset signaled
No operation
in progress
Equal
Equal
Equal
Equal
Equal
Equal
Equal
Equal
Successful
Successful
Zero
Zero
Interruption
pending/busy
Interruption
pending
Zero
All zeros Parameters loaded
Zero
Zero
Zero
Zero
Zero
Zero
Translation
available
Length equal
Length =< 256
Length =< 256
APPENDIX ~ CONDITION-CODE SETTINGS
The condition codes for the vector
facility are not included in this appen
dix. See the pUblication IBM System/370 Vector Operations, SA22-7125, for the
condition codes set by vector
instructions.
Some models may offer instructions which
set the condition code and do not appear
in this document, such as those provided
for assists or as part of special or
custom features.
Condition Code
1
< zero
< zero
Not zero,
no carry
< zero
< zero
Not zero CSW stored
Low
Low
Not equal
Low
Not equal
Low
Low
Low
Connected to
another CPU Connected to
another CPU < zero
Not zero CSW stored
CSW stored One First bit one Primary ASN not available
< zero
< zero
< zero
< zero
ST entry
invalid
Length low
> zero
> zero
Zero,
carry
> zero
> zero
2
Channel busy
Channel busy
High
High
High
High
High
High
> zero
3 Overflow Overflow Not zero,
carry
Not operational
Not operational
Not operational
Not operational Channel Not operational
working
Burst operation Not operational
terminated
First bit zero --
Secondary ASN Space-switch
not available event
or not
authorized
> zero
> zero
> zero
> zero
> zero PT entry
invalid
Length high Overflow Overflow Length
violation
Destructive
overlap
length > 256
Length > 256
Summary of Condition-Code Settings (Part 1 of 2)
Appendix C. Condition-Code Settings C-l

Condition Code
Instruction 0 1 2 3 OR Zero Not zero -- --
RESET REFERENCE BIT, RESET R bit zero, R bit zero, R bit one, R bit one,
REFERENCE BIT EXTENDED C bit zero C bit one C bit zero C bit one
RESUME I/O Successful ----Not operational
SET CLOCK Set Secure --Not operational
SHIFT AND ROUND DECIMAL Zero < zero > zero Overflow SHIFT LEFT (DOUBLE/SINGLE) Zero < zero > zero Overflow
SHIFT RIGHT (DOUBLE/SINGLE) Zero < zero > zero --
SIGNAL PROCESSOR Order accepted Status stored Busy Not operational
START I/O, START I/O FAST Successful CSW stored Busy Not operational
,RELEASE STORE CHANNEL ID ID stored CSW stored Busy Not operational STORE CLOCK Set Not set Error Not operational
SUBTRACT, SUBTRACT HALFWORD Zero < zero > zero Overflow
SUBTRACT DECIMAL Zero < zero > zero Overflow
SUBTRACT LOGICAL --Not zero, Zero, Not zero,
no carry carry carry
SUBTRACT NORMALIZED Zero < zero > zero --
SUBTRACT UNNORMALIZED Zero < zero > zero --
TEST AND SET Left bit zero Left bit one ----
TEST BLOCK Usable Not usable ----
TEST CHANNEL Available Interruption Burst mode Not operational
pending
TEST I/O Available CSW stored Busy Not operational
TEST PROTECTION Can fetch, Can fetch, Cannot fetch, Translation not
can store cannot store cannot store available
TEST UNDER MASK All zeros Mixed --All ones
TRANSLATE AND TEST All zeros Incomplete Complete -- ZERO AND ADD Zero < zero > zero Overflow
EXElanation:
-- Not applicable
> zero Result greater than zero
< zero Result less than zero
=< 256 Equal to, or less than, 256
> 256 Greater than 256
High First operand high
Low First operand low
length Length of first operand
Summary of Condition-Code Settings (Part 2 of 2)
C-2 System/370 Principles of Operation

Help

Mne- Op Page Name monic Characteristics Code No. MOVE INVERSE MVCIN ss MIl A I I ST E8 7-24
Instructions Arranged by Facility: Move Inverse
Mne- Op Page Name monic Characteristics Code No.
SET PREFIX SPX S MP P A SP $ B210 10-40 SIGNAL PROCESSOR SIGP RS C MP P $ R AE 10-46 STORE CPU ADDRESS STAP S MP P A SP ST B212 10-48 STORE PREFIX STPX S MP P A SP ST B211 10-49 Instructions Arranged by Facility: Multiprocessing
Mne- Op Page Name monic Characteristics Code No. INSERT PSW KEY IPK S PKIQ 1 G21 R B20B 10-8 SET PSW KEY FROM ADDRESS SPKA S PK Q B20A 10-41 Instructions Arranged by Facility: PSW-Key Handling
Mne- Op Page Name monic Characteristics Code No. CLEAR CHANNEL CLRCH S C RElp I ¢ f 9FOHE 13-16
Instructions Arranged by Facility: Recovery Extensions
Mne- Op Page Name monic Characteristics Code No. INSERT STORAGE KEY EXTENDED ISKE RRE EK P Al R B229 10-9 RESET REFERENCE BIT EXTENDED RRBE RRE C EK P Al B22A 10-37 SET STORAGE KEY EXTENDED SSKE RRE EK P Al ¢ B22B 10-45 Instructions Arranged by Facility: Storage-Key-Instruction Extensions
Mne- Op Page Name monic Characteristics Code No. RESUME I/O RIO S C SRlp I ¢ I 9C02* 13-26
Instructions Arranged by Facility: Suspend and Resume Appendix B. Lists of Instructions B-19

Mne- Op Page
Name monic Characteristics Code No.
TEST BLOCK TB RRE C TBlp Al III $ GOI R B22C 10-50 Instructions Arranged by Facility: Test Block
Mne- Op Page
Name monic Characteristics Code No. LOAD REAL ADDRESS LRA RX C TR P Al R B1 10-21 PURGE TLB PTLB S TR P $ B20D 10-36 RESET REFERENCE BIT RRB S C TR P Al SO B213 10-36 STORE THEN AND SYSTEM MASK STNSM S1 TR P A ST AC 10-50 STORE THEN OR SYSTEM MASK STOSM SI TR P A SP ST AD 10-50 Instructions Arranged by Facility: Translation B-20 System/370 Principles of Operation

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Extracted Text (may have errors)

Mne- Op Page Name monic Characteristics Code No. MOVE INVERSE MVCIN ss MIl A I I ST E8 7-24
Instructions Arranged by Facility: Move Inverse
Mne- Op Page Name monic Characteristics Code No.
SET PREFIX SPX S MP P A SP $ B210 10-40 SIGNAL PROCESSOR SIGP RS C MP P $ R AE 10-46 STORE CPU ADDRESS STAP S MP P A SP ST B212 10-48 STORE PREFIX STPX S MP P A SP ST B211 10-49 Instructions Arranged by Facility: Multiprocessing
Mne- Op Page Name monic Characteristics Code No. INSERT PSW KEY IPK S PKIQ 1 G21 R B20B 10-8 SET PSW KEY FROM ADDRESS SPKA S PK Q B20A 10-41 Instructions Arranged by Facility: PSW-Key Handling
Mne- Op Page Name monic Characteristics Code No. CLEAR CHANNEL CLRCH S C RElp I ¢ f 9FOHE 13-16
Instructions Arranged by Facility: Recovery Extensions
Mne- Op Page Name monic Characteristics Code No. INSERT STORAGE KEY EXTENDED ISKE RRE EK P Al R B229 10-9 RESET REFERENCE BIT EXTENDED RRBE RRE C EK P Al B22A 10-37 SET STORAGE KEY EXTENDED SSKE RRE EK P Al ¢ B22B 10-45 Instructions Arranged by Facility: Storage-Key-Instruction Extensions
Mne- Op Page Name monic Characteristics Code No. RESUME I/O RIO S C SRlp I ¢ I 9C02* 13-26
Instructions Arranged by Facility: Suspend and Resume Appendix B. Lists of Instructions B-19

Mne- Op Page
Name monic Characteristics Code No.
TEST BLOCK TB RRE C TBlp Al III $ GOI R B22C 10-50 Instructions Arranged by Facility: Test Block
Mne- Op Page
Name monic Characteristics Code No. LOAD REAL ADDRESS LRA RX C TR P Al R B1 10-21 PURGE TLB PTLB S TR P $ B20D 10-36 RESET REFERENCE BIT RRB S C TR P Al SO B213 10-36 STORE THEN AND SYSTEM MASK STNSM S1 TR P A ST AC 10-50 STORE THEN OR SYSTEM MASK STOSM SI TR P A SP ST AD 10-50 Instructions Arranged by Facility: Translation B-20 System/370 Principles of Operation

APPENOIX ~ FACILITIES
Commercial Instruction Set •...•.•••.••••..••••••••••.•.•.. 0-1 Other Facilities •.•..•••••.••.•.••••.•••••••..••••••••.•.• 0-1 Branch and Save .•.....•..•....•......•••••...••••••.•.•. 0-2 Channel Indirect Oata Addressing •...••••..•••.•.••.•.... 0-2 Channel-Set Switching .•......•..••.•••••.....•.•....••.. 0-2 Clear I/O ••...........•.•.•.•.•.•••..•.•...........•.... 0-2 Command Retry •..••..•••••....•..••••••••••..•••.••.••••. 0-2 Conditional Swapping .•••.•.....•••••.•••....••.....••.•. 0-2 CPU Timer and Clock Comparator .•••.•..•.•......•........ 0-2 Direct Control ..•••....•.•.•..•.•.••.•.••••••..•........ 0-2 Dual-Address Space (OAS) •.•.....•••.••••.•.•..••...•..•. 0-2 Extended ........•......•.••.....••....•....••.•..•.....• 0-3 Extended-Precision Floating Point ...................•... 0-3 Extended Real Addressing .....•...•..•......•..•...•.•... 0-3 External Signals ••.....•••....••.•....•••..••••.•••..... 0-3 Fast Release •...•••.•..........•••••.•••.•••...•••..•••. 0-3 Floating Point •.•.•..............•..•..•....•..•.•.•••.. 0-4 Halt Device ..••.•.•...•.•.....•..•.•••••.........•..•... 0-4 I/O Extended Logout .......•..••..••..••....•••.•...••.•. 0-4 Limited Channel Logout ........•••••..•••••..•••.....•.•. 0-4 Move Inverse ...............•...••••.••••...••...••..•... 0-4 Multiprocessing .....................••••...•............ 0-4 PSW-Key Handling •....•.....•••..•.••.•••.••••.•..•..•.•. 0-4 Recovery Extensions ....•.•.....•.••.•••••••••••..•..•... 0-4 Segment Protection ....•...•..••.•....•••..•••..••..•.•.. 0-4 Service Signal ....••.••..••.•....•.•.•................•. 0-4 Start-I/O-Fast Queuing ..•.......•..••••..•.•••.......... 0-4 Storage-Key-Instruction Extensions ....•.........•...•... 0-5 Storage-Key 4K-Byte Block ....•..•....•••••.••....•....•. 0-5 Suspend and Resume ....•........•...•..••................ 0-5 Test Block .......•....................•.......•......... 0-5 Translation ••••.•........•..•...••••.••......•••.•.•••.. 0-5 Vector •...•.•...•..............•.••.•.•.•..••••.••.•..•. 0-5 31-Bi t IOAWs •...••....•.............••.•..•••..•.•.•.••. 0-5 This appendix lists the facilities in
System/370. Every system includes a
CPU, main storage, and the capability
for at least one byte-multiplexer,
block-multiplexer, or selector channel.
The capability may be implemented by
means of a separate physical unit or may
be provided by sharing the physical unit
with the CPU.
control bit (if block multiplexing
is provided), for the interrupt-key
and interval-timer masks, for chan
nel masks associated with installed
channels, for monitor masks, for
control of installed machine
check-handling facilities, and for
the IOEL control (if an installed
channel has the I/O-extended-Iogout
facility)
COMMERCIAL INSTRUCTION SET Every CPU incorporates the commercial
instruction set (listed in Appendix B)
and the associated basic computing func
tions, including: • Byte-oriented operands • General registers • Basic-control (BC) mode • Control registers, with bit posi
tions for the block-multiplexing- • Key-controlled protection • Interval timer • TOO clock • Basic operator facilities OTHER FACILITIES
Additionally, the following facilities
are available:
Appendix D. Facilities 0-1

BRANCH AND SAVE
Includes the BRANCH AND SAVE (BAS and
BASR) instruction. CHANNEL INDIRECT DATA ADDRESSING
Includes indirect-data-address words and
the associated CCW flag, which facili
tate storage addressing when virtual
addresses are used. CHANNEL-SET SWITCHING Provides the ability to connect a chan
nel set to any CPU in a multiprocessing
configuration. It includes the
instructions CONNECT CHANNEL SET and DISCONNECT CHANNEL SET. CLEAR I/O Provides the clear-I/O (CLRIO) function
on a channel when the CLEAR I/O instruc
tion is executed. When the CLRIO func
tion is not implemented, CLEAR I/O is
executed as TEST I/O. COMMAND RETRY Provides the capability in a channel to
retry a command without the occurrence
of an I/O interruption. The retry is
initiated by the control unit. CONDITIONAL SWAPPING Includes the instructions COMPARE AND SWAP and COMPARE DOUBLE AND SWAP. CPU TIMER AND CLOCK COMPARATOR Includes the clock comparator, the CPU timer, the associated extensions to
external interruption, control-register
positions for the clock-comparator and CPU-timer masks, and the instructions
SET CLOCK COMPARATOR, STORE CLOCK COMPA RATOR, SET CPU TIMER, and STORE CPU TIMER.
D-2 System/370 Principles of Operation DIRECT CONTROL Includes the external-signal facility
and the read-write-direct facility,
which contains the instructions READ DIRECT and WRITE DIRECT. DUAL-ADDRESS SPACE (DAS)
Includes the following:
1. Dual-space control, which includes:
a. An address-space control, PSW bit 16
b. A primary ASN, bits 16-31 of
control register 4
c. A secondary ASN, bits 16-31 of
control register 3
d. A secondary-segment-table
designation, in control regis
ter 7
2. DAS authorization mechanisms, which
include the following:
a. An extraction-authority
control, bit 4 of control
register 0 b. A PSW-key mask, bits 0-15 of
control register 3
c. A secondary-space control, bit
5 of control register 0 d. A subsystem-linkage control,
bit 0 of control register 5
e. An ASN-translation control, bit
12 of control register 14
f. An authorization index, bits 0-15 of control register 4
g. A space-switch-event-control
bit, bit 31 of control register
1
3. PC-number translation, which uses
the linkage-table designation in
control register 5
4. ASN translation, which uses an
ASN-first-table origin, bits 20-31 of control register 14
5. ASN authorization
6. DAS tracing
7. The following instructions: EXTRACT PRIMARY ASN (EPAR) EXTRACT SECONDARY ASN (ESAR)
INSERT ADDRESS SPACE CONTROL (lAC) INSERT VIRTUAL STORAGE KEY (IVSK)

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