1.-6. Exceptions with the same priority as the priority of program
interruption conditions for the general case.
7.A Access exceptions for second instruction halfword.
7.B.lOperation exception if the dual-address-space facility is not
installed.
7.B.2 Special-operation exception due toOAT being off, the CPU being in secondary-space mode, or the subsystem-linkage
control bit in control register 5 being zero.
8.A Trace exceptions.
8.B.l Privileged-operation exception due to attempt to set the
supervisor state when in the problem state.
8.B.2 Specification exception due to nonzero value in bits0-7 of
general registerR
2
• 8.B.3 Special-operation exception due to the ASN-translation con
trol, bit 12 of control register14, being zero (PT-ss only).
8.B.4 ASN-translation exceptions (PT-ss only).
8.B.5 Primary-authority exception due to authority-table entry
being outside table (PT-55 only).
8.B.6 Addressing exception for access to authority-table entry
(PT-ss only).
8.B.7 Primary-authority exception due to P bit in authority-table
entry being zero (PT-ss only).
9. Space-switch event (PT-ss on!y).
Priority of Execution: PROGRAM TRANSFER
Programming Notes
1. The operation of PROGRAM TRANSFER
(PT) is such that it may be used to
restore theCPU to the state saved
by a previous PROGRAMCALL. This
restoration is accomp!ished by
issuing PT 3,14. Though general
registers 3 and 14 are not restored
to their original values, the PASN,
PSW-key mask, problem-state bit,
and instruction address are
restored, and the authorization
index, PSTD, and LTD are made
consistent with the restored PASN.
2.With proper authority, and while
executing in a common area, PROGRAM
TRANSFER may beused to change the
primary address space to any
desired space. The secondary
address space is also changed to be
the same as the new primary address
space.3. Unlike the RR-format branch in
structions, a value of zero in theR2 field for PROGRAM TRANSFER
designates genera! register0, and
branching occurs.Chapter 10. Control Instructions 10-33
interruption conditions for the general case.
7.A Access exceptions for second instruction halfword.
7.B.l
installed.
7.B.2 Special-operation exception due to
control bit in control register 5 being zero.
8.A Trace exceptions.
8.B.l Privileged-operation exception due to attempt to set the
supervisor state when in the problem state.
8.B.2 Specification exception due to nonzero value in bits
general register
2
•
trol, bit 12 of control register
8.B.4 ASN-translation exceptions (PT-ss only).
8.B.5 Primary-authority exception due to authority-table entry
being outside table (PT-55 only).
8.B.6 Addressing exception for access to authority-table entry
(PT-ss only).
8.B.7 Primary-authority exception due to P bit in authority-table
entry being zero (PT-ss only).
9. Space-switch event (PT-ss on!y).
Priority of Execution: PROGRAM TRANSFER
Programming Notes
1. The operation of PROGRAM TRANSFER
(PT) is such that it may be used to
restore the
by a previous PROGRAM
restoration is accomp!ished by
issuing PT 3,14. Though general
registers 3 and 14 are not restored
to their original values, the PASN,
PSW-key mask, problem-state bit,
and instruction address are
restored, and the authorization
index, PSTD, and LTD are made
consistent with the restored PASN.
2.
executing in a common area, PROGRAM
TRANSFER may be
primary address space to any
desired space. The secondary
address space is also changed to be
the same as the new primary address
space.
structions, a value of zero in the
designates genera! register
branching occurs.
