A
A (ADD) binary instruction 7-7
absolute address 3-5
absolute storage 3-5
access-control bits in storage key 3-6
access exceptions 6-28,6-33
priority of 6-33
recognition of 6-28
access key 3-8
for channel-program execution 3-9
for CPU 3-8
access to storage 5-24
(See also reference)
AD (ADD NORMALIZED) instruction 9-6
example A-36
ADD (A,AR) binary instructions 7-7
ADD DECIMAL (AP) instruction 8-5
example A-30 ADD HALFWORD (AH) instruction 7-7
example A-8
ADD LOGICAL (AL,ALR) instructions 7-8
ADD NORMALIZED (AD,ADR,AE,AER,AXR)
instructions 9-6
example A-36
ADD UNHORMALIZED (AU,AUR,AW,AWR)
instructions 9-7
example A-36
address 3-2
absolute 3-5
arithmetic 3-6,5-5
unsigned binary 7-3
base (See base address)
branch (See branch address)
channel 13-8,13-15
channel-set 4-43
comparison 12-1
controls for 12-1
effect on CPU state 4-2
CPU (See CPU address)
device 13-8,13-15
effective (See effective address)
failing-storage (See failing-storage
address)
format 3-3
generation 5-5
for storage addressing 3-2 I/O (See I/O address)
instruction (See instruction
address)
invalid 6-15
logical (See logical address)
numbering of for byte locations 3-2
PER (See PER address)
prefixing (See prefix)
primary virtual (See primary virtual
address)
real 3-5
secondary virtual (See secondary
virtual address)
storage 3-2
summary information 3-38
translation (See dynamic address
translation, prefix)
types 3-5
virtual 3-5
wraparound (See wraparound)
address space 3-12
control bit
in PSW 4-7
use in address translation 3-22
created by OAT 3-20 number (See ASN)
addressing exception 6-15
as an access exception 6-28,6-33
ADR (ADD NORMALIZED) instruction 9-6
AE (ADD NORMALIZED) instruction 9-6
example A-36
AER (ADD NORMALIZED) instruction 9-6
AFT (ASH first table) 3-14
AFTE (ASN-first-table entry) 3-14 AFTO (ASN-first-table origin) 3-13
AFX (ASH-first-table index) 3-13
invalid bit 3-14
translation exception 6-18
AH (ADD HALFWORD) instruction 7-7
example A-8
AKM (authorization key mask) 5-22
AL (ADD LOGICAL) instruction 7-8
alert, I/O-error (in limited channel
logout) 13-82
alert (class of machine-check condition)
11-12
allowed interruptions 6-6
ALR (ADD LOGICAL) instruction 7-8
alter-and-display controls 12-2
alteration
general-register (PER event) 4-20 storage (PER event) 4-19 AND (N,NC,NI,NR) instructions 7-8
examples A-8
AP (ADD DECIMAL) instruction 8-5
example A-30 AR (ADD) binary instruction 7-7
architectural mode 1-1
compatibility 1-3
arithmetic
address (See address arithmetic)
binary 7-3
examples A-2
decimal 8-2
examples A-5,A-30
floating-point 9-1
examples A-5,A-36
logical (unsigned binary) 7-3
examples A-4
ASCII character code, handled by archi­
tecture iv
ASN (address-space number) 3-12
as part of DAS 5-14
authorization 3-17
first table (AFT) 3-14
index (AFX) 3-13
origin (AFTO) 3-13
in entry-table entry 5-22
second table (AST) 3-14
index (ASX) 3-13
origin (ASTO) 3-14
translation 3-13
exceptions 6-35
specification exception 6-18
translation-control bit 3-13,5-18
assembler language A-7
instruction formats in (See instruc­
tion lists and page numbers in
Appendix B)
assigned storage locations 3-41
Index X-I

AST (ASN second table) 3-14 ASTE (ASN-second-table entry) 3-14 ASTO (ASN-second-table origin) 3-14 ASX (ASN-second-table index) 3-13 invalid bit 3-14
translation exception 6-18
asynchronous fixed-logout-control bit
11-29
asynchronous logout 11-28
asynchronous machine-check
extended-logout-control bit 11-29
AT (authority table) 5-18
ATL (authority-table length) 3-14 ATO (authority-table origin) 3-14
attached segment-table or page-table
entry 3-32
attachment of I/O devices 13-2
attention (unit status) 13-64
AU (ADD UNNORMALIZED) instruction 9-7
example A-36
AUR (ADD UNNORMALIZED) instruction 9-7
authority table (AT) 5-18
designation 3-14
authorization ASN 3-17
index (AX) 3-17,5-18
key mask (AKM) 5-22
mechanisms 5-17
authorization mechanisms, summary of 5-20 auxiliary storage 3-2,3-20 availability (characteristic of a
system) 1-4
available state (I/O system) 13-10 AW (ADD UNNORMALIZED) instruction 9-7
AWR (ADD UNNORMALIZED) instruction 9-7
AX (authorization index) 5-18
AXR (ADD NORMALIZED) instruction 9-6
B
B field of instruction 5-5
backed-up bit (machine-check condition)
11-19
backup, processing (synchronous
machine-check condition) 11-19
BAL (BRANCH AND LINK) instruction 7-9
examples A-8
BALR (BRANCH AND LINK) instruction 7-9
examples A-8 BAS (BRANCH AND SAVE) instruction 7-9
example A-8
base address 5-5
register for 2-4
basic control (See BC mode)
basic operator facilities 12-1
basic sense command 13-51 BASR (BRANCH AND SAVE) instruction 7-9
example A-8 BC (basic-control) mode 4-4
program conversion to EC mode 10-46 PSW format in 4-8 BC (BRANCH ON CONDITION) instruction 7-10 example A-10 BCR (BRANCH ON CONDITION) instruction 7-10 BCT (BRANCH ON COUNT) instruction 7-11
example A-I0 BCTR (BRANCH ON COUNT) instruction 7-11
example A-I0 binary (See also fixed point)
X-2 System/370 Principles of Operation arithmetic 7-3
examples A-2 negative zero 7-2
number representation 7-2
examples A-2
overflow 7-3
example A-2
sign bit 7-2
binary-to-decimal conversion 7-17
example A-16
bit 3-2
numbering of within a group of bytes
3-3
block-concurrent storage references
5-31
block-multiplexer channel 13-5
block-multiplexing-control bit 13-5
effect on CLEAR I/O instruction of
13-17
effect on START I/O FAST RELEASE instruction of 13-27
block of I/O data 13-37
incorrect length for 13-70 self-describing 13-42
block of storage 3-5 (See also page)
testing for usability of 10-50 borrow 7-37
boundary alignment 3-3
for instructions 5-3
branch address 5-6 BRANCH AND LINK (BAL,BALR) instructions
7-9
examples A-8 BRANCH AND SAVE (BAS,BASR) instructions
7-9
examples A-8
branch-and-save facility D-2 BRANCH ON CONDITION (BC,BCR) instructions 7-10 example A-10 BRANCH ON COUNT (BCT,BCTR) instructions
7-11
example A-10 BRANCH ON INDEX HIGH (BXH) instruction
7-11
examples A-II BRANCH ON INDEX LOW OR EQUAL (BXLE)
instruction 7-11
examples A-12
branching
branch address generation 5-6
to perform decision making, loop
control, and subroutine linkage 5-6
buffer storage (cache) 3-2
burst mode (channel operation) 13-4
bus-out check (bit in I/O-sense data)
13-51
busy
as unit status (I/O) 13-65 in I/O operations 13-7
in SIGNAL PROCESSOR 4-40 BXH (BRANCH ON INDEX HIGH) instruction
7-11
examples A-II BXLE (BRANCH ON INDEX LOW OR EQUAL)
instruction 7-il
examples A-12
bypassing POST and WAIT A-42
byte 3-2
numbering of in storage 3-2
byte index (BX) 3-21
byte-multiplex mode (channel operation)
13-4