length (LTL) 5-21
origin (LTO) 5-21
LM (LOAD MULTIPLE) instruction 7-22
LNDR (LOAD NEGATIVE) floating-point
instruction 9-11
LNER (LOAD NEGATIVE) floating-point
instruction 9-11
LNR (LOAD NEGATIVE) binary instruction
7-22 LOAD (L,LR) binary instructions 7-20 example A-20 LOAD (LD,LDR,LE,LER) floating-point
instructions 9-10 LOAD ADDRESS (LA) instruction 7-21
examples A-20 LOAD ADDRESS SPACE PARAMETERS (LASP) instruction 10-12 LOAD AND TEST (LTDR,LTER) floating-point
instructions 9-11 LOAD AND TEST (LTR) binary instruction
7-21
load-clear key LOAD COMPLEMENT floating-point LOAD COMPLEMENT 7-21
12-3
(LCDR,LCER)
instructions 9-11
(LCR) binary instruction LOAD CONTROL (LCTL) instruction 10-20 LOAD HALFWORD (LH) instruction 7-22
examples A-20 load indicator 12-3 LOAD MULTIPLE (LM) instruction 7-22 LOAD NEGATIVE (LNDR,LNER) floating-point
instructions 9-11 LOAD NEGATIVE (LNR) binary instruction
7-22
load-normal key 12-3 LOAD POSITIVE (LPDR,LPER) floating-point
instructions 9-12 LOAD POSITIVE (LPR) binary instruction
7-22 LOAD PSW (LPSW) instruction 10-20 LOAD REAL ADDRESS (LRA) instruction 10-21 LOAD ROUNDED (LRDR,LRER) instructions
9-12
load state 4-2,4-3
during IPL 4-35
load-unit-address controls 12-3
loading, initial (See IML, IPL) location 3-2 (See also address)
not available in configuration 6-15
location 80 (for interval timer) 4-29
location 84 (in tracing) 4-13
lock A-42
example with FIFO queuing A-45
example with LIFO queuing A-44
logical
arithmetic (unsigned binary) 7-3
comparison 7-4
connective AND 7-8
EXCLUSIVE OR 7-18 OR 7-30 data 7-2
logical address 3-6
handling by DAT 3-22
logout
channel 13-80 extended machine-check 11-28
address 11-29
length of 11-23
validity bit for 11-23
fixed
assigned storage locations for
3-44
channel (See full channel logout)
machine-check 11-28 I/O extended (See IOEL) limited channel (See limited channel
logout)
logout pending (bit in CSW) 13-63
long floating-point number 9-2
long I/O block 13-70 loop control 5-6
loop of interruptions (See string of
interruptions)
low-address protection 3-9
control bit 3-9
exception for 6-23 LPDR (LOAD POSITIVE) floating-point
instruction 9-12 LPER (LOAD POSITIVE) floating-point
instruction 9-12 LPR (LOAD POSITIVE) binary instruction
7-22 LPSW (LOAD PSW) instruction 10-20 LR (LOAD) binary instruction 7-20 LRA (LOAD REAL ADDRESS) instruction 10-21 LRDR (LOAD ROUNDED) instruction 9-12
LRER (LOAD ROUNDED) instruction 9-12
LT (linkage table) 5-21
LTD (linkage-table designation) 5-21
LTDR (LOAD AND TEST) floating-point
instruction 9-11
LTER (LOAD AND TEST) floating-point
instruction 9-11
LTL (linkage-table length) 5-21 LTO (linkage-table origin) 5-21
LTR (LOAD AND TEST) binary instruction
7-21
LX (linkage index) 5-21
invalid bit 5-21
translation exception 6-20 M
M (mega) iv
M (MULTIPLY) binary instruction 7-28
example A-24
machine check 11-2 (See also malfunction)
extended logout (MCEL) 11-28
address 11-29
length of 11-23
validity bit for 11-23
handling of malfunction detected as
part of I/O 11-5
interruption 6-14,11-11
action 11-12
code (MCIC) 3-44,11-15
floating conditions 11-27
mask in BC-mode PSW 4-8
mask in EC-mode PSW 4-6
subclass masks in control register
11-27
logout 11-28
control bits for 11-29
mask, in EC-mode PSW 4-6
mask in BC-mode PSW 4-8
main storage 3-2 (See also storage) effect of power-on reset on 4-35
shared (in multiprocessing) 4-38
malfunction 11-2
correction of 11-2
Index X-13

effect on manual operation 12-1
from DIAGNOSE instruction 10-5 indication of 11-5
machine-check handling for when detected as part of I/O 11-5
malfunction alert (external
interruption) 6-12
when entering check-stop state 11-11
manual indicator 12-3 (See also stopped state)
manual operation 12-1
controls
address-compare 12-1
alter-and-display 12-2
IML 12-2
interval-timer 12-3
load-unit-address 12-3
power 12-3
rate 12-4 TOD-clock 12-5
effect on CPU signaling 4-40 keys
interrupt 12-2
load-clear 12-3
load-normal 12-3
restart 12-4
start 12-4
stop 12-4
store-status 12-5
system-reset-clear 12-5
system-reset-normal 12-5
masks 6-6 (See also I/O interruption, inter­
ruption)
channel 6-14 in BRANCH ON CONDITION instruction 7-10 in COMPARE LOGICAL CHARACTERS UNDER
MASK instruction 7-15
in INSERT CHARACTERS UNDER MASK
instruction 7-20 in PSW BC mode 4-8 EC mode 4-6
in STORE CHARACTERS UNDER MASK
instruction 7-35
monitor 6-21 PER-event 4-16 PER general-register 4-16
program-interruption 6-15
subclass
external-interruption 6-10 machine-check-interruption 11-27
mathematical assists, publication refer-
enced v
maximum negative number 7-2 MC (MONITOR CALL) instruction 7-23 MCEL (See machine check, extended
logout) MCIC (machine-check-interruption code)
3-44,11-15
MD (MULTIPLY) floating-point instruction
9-13
MDR (MULTIPLY) floating-point instruc­
tion 9-13
example A-38
ME (MULTIPLY) floating-point instruction
9-13
measurement byte
assigned storage locations for 3-44
in I/O-communication area 13-83
storing of 13-62
MER (MULTIPLY) floating-point instruc­
tion 9-13
X-14 System/370 Principles of Operation message byte (in EDIT) 8-7
MH (MULTIPLY HALFWORD) instruction 7-29
example A-24
microprogram (initial loading of) 12-2
mode BC (See BC mode)
burst (channel operation) 13-4
byte-multiplex (channel operation)
13-4 EC (See EC mode) I primary-space 3-22
as part of DAS 5-14
real 3-22
secondary-space 3-22
as part of DAS 5-14
translation 3-22
mode requirements for DAS 5-17
model, channel 13-32
model number (in CPU ID) 10-48 modifier bits (in CCW command code)
13-39 MONITOR CALL (MC) instruction 7-23
monitor-class number 6-21
assigned storage locations for 3-43
monitor code 6-21
assigned storage locations for 3-43
monitor event 6-21
monitor masks 6-21
monitoring
for PER events (See PER) with MONITOR CALL 6-21,7-23 MOVE (MVC,MVI) instructions 7-23
examples A-18,A-21
move instructions provided by DAS 5-15 MOVE INVERSE (MVCIN) instruction 7-24
example A-22
move-inverse facility D-4,7-24 MOVE LONG (MVCL) instruction 7-24
examples A-22 MOVE NUMERICS (MVN) instruction 7-27
example A-23 MOVE TO PRIMARY (MVCP) instruction
10-22 MOVE TO SECONDARY (MVCS) instruction
10-22 MOVE WITH KEY (MVCK) instruction 10-24 MOVE WITH OFFSET (MVO) instruction 7-27
example A-23 MOVE ZONES (MVZ) instruction 7-28
example A-24 MP (MULTIPLY DECIMAL) instruction 8-10 example A-34
MR (MULTIPLY) binary instruction 7-28
example A-24
multiple-access storage references 5-31
multiplexer channel 13-5 MULTIPLY (M,MR) binary instructions
7-28
examples A-24 MULTIPLY (MD,MDR,ME,MER,MXD,MXDR,MXR)
floating-point instructions 9-13
example A-38 MULTIPLY DECIMAL (MP) instruction 8-10 example A-34 MULTIPLY HALFWORD (MH) instruction 7-29
example A-24
multiprocessing 4-37 facility D-4
manual operations for 12-6
programming considerations for A-40,8-3 programming examples A-40 timing-facility interruptions for
4-26