Vector-Facility Source
Bit 13 (VS) of the machine-check­
interruption code, when one, indicates
that the vector facility is the source
of the reported machine-check condition.
Vector-facility source is reported
together with instruction-processing
damage. When this bit is one, the
contents of vector-facility registers
may have been damaged.
This bit may be set to one regardless of
whether the vector-control bit, bit 14
of control register 0, is one or zero.
Bit 13 is not meaningful when vector­
facility failure is reported.
Backed !!.e Bit 14 (B), when one, indicates that the
point of interruption is at a checkpoint
before the point of error. This bit is
meaningful only when the instruction­
processing-damage bit, bit 1, is also
set to one. The presence and extent of
the capability to indicate a backed-up
condition depend on the model.
Delayed
Bit 15 (D), when one, indicates that
some or all of the machine-check condi­
tions were delayed in being reported
because the CPU was disabled for that
type of interruption at the time the
condition occurred. The bit mayor may
not apply to floating machine-check
interruptions. The presence and extent
of the capability to indicate a delayed
condition depend on the model.
Delayed Access Exception
Bit 34 (DA), when one, indicates that an
access exception was detected during a
storage access using OAT when no such
exception was detected by an earlier
test for access exceptions.
Bit 34 is a modifier to instruction­
processing damage (bit 1) and is mean­
ingful only when bit 1 of the machine­
check-interruption code is one. When
bit 1 is zero, bit 34 has no meaning.
The presence and extent of reporting
delayed access exception depend on the
model.
Programming Note The occurrence of a delayed access
exception normally indicates that the
program is uSlng an improper procedure
to update the OAT tables. SYNCHRONOUS MACHINE-CHECK-INTERRUPTION CONDITIONS The instruction-processing damage and
backed-up bits, bits 1 and 14 of the
machine-cheek-interruption code, identi­ fy, in combination, two conditions.
Bit 1 Bit 1i Name of Condition
1
1
o
1 Processing damage Processing backup
Processing Backup
The processing-backup condition indi­
cates that the point of interruption is prior to the point, or points, of error.
This is a nullifying exigent condition.
When all of the other CPU-related-damage
subclasses and modifiers of the
machine-cheek-interruption code are zero
and all of the validity bits associated
with CPU status are indicated as valid,
the machine has successfully returned to
a checkpoint prior to the malfunction,
and no damage has yet occurred to the
CPU.
The subclass bits which must be zero for
this to be the case are as follows:
MCIC Bit
o
3
4
6
Name
System damage
Interval-timer damage
Timing-facility damage
Vector-facility failure
The subclass-modifier bits which must be
zero for this to be the case are as
follows:
MCIC Bit
13
34
Vector-facility source
Delayed-access exception
The validity bits in the machine-check­
interruption code which must be one for
this to be the case are as follows:
Chapter 11. Machine-Check Handling 11-19

MCIC .Ilil 20 21
22
23
27
28
29
31
46
47
Programming Note
Fields Covered ~ .Ilil PSW EMWP bits PSW mask and key PSW program mask and
condition code PSW instruction address
Floating-point registers
General registers Control registers Storage logical validity (result fields within
current checkpoint
interval> CPU timer Clock comparator
The processing-backup condition is reported rather than system recovery to
indicate that a malfunction or failure
stands in the way of continued operation
of the CPU. The malfunction has not
been circumvented, and damage would have
occurred if instruction processing had
continued.
Processing Damage
The processing-damage condition indi­ cates that damage has occurred to the
instruction processing of the CPU. The
point of interruption is a point beyond
some or all of the points of damage. Processing damage is a terminating
exigent condition; therefore, the
contents of result fields may be unpre­
dictable and still indicated as valid. Processing damage may include malfunc­
tions in program-event recording, moni­
tor call, and dynamic address
translation. Processing damage causes
any supervisor-call-interruption condi­
tion and program-interruption condition
to be discarded. However, the contents
of the old PSW and interruption-code
locations for these interruptions may be
set to unpredictable values. STORAGE ERRORS Bits 16-18 of the machine-check­
interruption code are used to indicate
an invalid CBC or a near-valid CBC detected in main storage or an invalid CBC in a storage key. Bit 19, storage degradation, may be indicated concur­
rently with bit 17. The failing­
storage-address field, when indicated as 11-20 System/370 Principles of Operation
valid, identifies a location within the
storage checking block containing the
error, or, for storage-key error uncor­
rected, within the block associated with the storage key. Bit 32, indirect stor­
age error, may be set to one to indicate
that the location designated by the
failing-storage address is not the
original source of the error.
The storage-error-uncorrected and
storage-key-error-uncorrected bits do
not in themselves indicate the occur­
rence of damage because the error
detected may not have affected a result.
The portion of the configuration
affected by an invalid CBC is indicated
in the subclass field of the machine­
check-interruption code.
Storage errors detected for a channel,
when indicated as I/O-error conditions,
may also be reported as (1) system
recovery, (2) external damage with the
external-damage code valid or invalid,
or (3) external secondary report. CBC errors that occur in storage or in the
storage key and that are detected on
prefetched or unused data for a CPU program mayor may not be reported,
depending on the model.
Storage Error Uncorrected
Bit 16 (SE), when one, indicates that a checking block in main storage contained
invalid CBC and that the information
could not be corrected. The contents of
the checking block in main storage have
not been changed. The location reported
may have been accessed or prefetched for
this CPU or another CPU or a channel, or
it may have been accessed as the result
of a model-dependent storage access.
Storage Error Corrected Bit 17 (SC), when one, indicates that a checking block in main storage contained
near-valid CBC and that the information
has been corrected before being used.
Depending on the model, the contents of
the checking block in main storage may
or may not have been restored to valid CBC. The location reported may have
been accessed or prefetched for this CPU or for another CPU or for a channel, or
it may have been accessed as the result
of a model-dependent storage access.
The presence and extent of the storage­
error-correction capability depend on
the model. This indication mayor may
not be accompanied by an indication of
storage degradation, bit 19 (OS).