code is stored
134-135.
136-139 (Real Address) at locations
Supervisor-CalI-Interruption
Identification: During a supervisor-call interruption in
the EC mode, the instruction­
length code is stored in bit
positions 5 and 6 of location
137, and the interruption code
is stored at locations 138-139. Zeros are stored at location 136
and in the remaining bit posi­ tions of location 137. 140-143 (Real Address)
Proqram-Interruption Identifi­
cation: During a program inter­
ruption in the EC mode, the
instruction-length code is
stored in bit positions 5 and 6
of location 141, and the inter­
ruption code is stored at
locations 142-143. Zeros are
stored at location 140 and in
the remaining bit positions of
location 141.
144-147 (Real Address)
Translation-Exception Identifi­
cation: During a program inter­
ruption due to a segment­
translation exception or a page-translation exception, the
segment-index and page-index
portion of the virtual address
causing the exception is stored at locations 144-147. This
address is sometimes referred to as the translation-exception
address. When 2K-byte pages are
used, the rightmost 11 bits of
the address are unpredictable.
When 4K-byte pages are used, the
rightmost 12 bits of the address
are unpredictable. Bits 1-7 of
location 144 are set to zeros.
When DAS is installed, bit 0 of
location 144 is set to zero if
the translation was relative to
the primary segment table desig­
nated by control register 1, or
it is set to one if the trans­
lation was relative to the
secondary segment table desig­
nated by control register 7.
When DAS is not installed, bit 0 of location 144 is set to zero.
During a program interruption due to an AFX-translation, ASX­
translation, primary-authority,
or secondary-authority excep­
tion, the ASN being translated
is stored at locations 146-147. Zeros are stored at locations
144-145.
During a program interruption
for a space-switch event, the
old PASN, which is in bits 16-31
of control register 4 before the
execution of a space-switching PROGRAM CALL or PROGRAM TRANSFER
instruction, is stored at
locations 146-147. The old
space-switch-event-control bit is stored in bit position 0, and
zeros are stored in bit posi­
tions 1-15 of locations 144-145.
During a program interruption
due to an LX-translation or EX­
translation exception, the PC
number is stored in bit posi­ tions 12-31 of the word at
locations 144-147. Bits 0-11 are set to zeros.
In all
locations
when the
EC mode.
cases,
144-147
old PSW
148-149 (Real Address)
storing at
only occurs
specifies the
Monitor-Class Number: During a program interruption due to a
monitor event, the monitor-class
number is stored at location
149, and zeros are stored at location 148. 150-151 (Real Address)
PER Code: During a program
interruption due to a PER event,
the PER code is stored in bit positions 0-3 of location 150. Zeros are stored in bit posi­
tions 4-7 of location 150 and
bit positions 0-7 of location
151. This field can be stored
only when the instruction caus­
ing the PER condition was
executed under the control of a PSW specifying the EC mode.
152-155 (Real Address)
PER Address: During a program
interruption due to a program
event, the PER address is stored
at locations 153-155, and zeros
are stored at location 152.
This field can be stored only
when the instruction causing the
PER condition was executed under
the control of a PSW specifying
the EC mode.
156-159 (Real Address)
Monitor Code: During a program
interruption due to a monitor
event, the monitor code is
stored at locations 157-159, and
zeros are stored at location
156.
Chapter 3. storage 3-43

168-171 (Real Address)
Channel ID: The channel­ identification information is
stored at locations 168-171
during the execution of STORE CHANNEL ID.
172-175 (Real Address) IOEL Address: The 1/0- extended-logout address is fetched from locations 173-175 during the I/O-extended-Iogout operation. The contents of
location 172 are ignored.
176-179 (Real Address)
Limited Channel Logout: The limited-channel-logout informa­ tion is stored at locations
176-179. This field may be stored only when the CSW or a
portion of the CSW is stored.
185 (Real Address) Measurement Byte: During an I/O interruption in the EC mode, the measurement byte is stored at
location 185. A nonzero value
for the measurement byte is part
of the start-I/O-fast-queuing
facility. When this facility is not installed, zeros are stored.
186-187 (Real Address) 1/0 Address: During an 1/0 interruption in the EC mode and
at the conclusion of an IPL in
the EC mode, the I/O address is stored at locations 186-187.
216-223 (Absolute Address)
Store-Status CPU-Timer Save Area: During the execution----o:F the store-status operation, the
contents of the CPU timer, if
the CPU-timer and clock-
comparator facility is
installed, are stored at
locations 216-223.
216-223 (Real Address)
Machine-Check CPU-Timer Save Area: During a machine-check
interruption, the contents of
the CPU timer, if the CPU-timer
and clock-comparator facility is installed, are stored at
locations 216-223.
224-231 (Absolute Address)
Store-Status Clock-Comparator Save Area: During the execution
of the store-status operation, the contents of the clock compa­
rator, if the CPU-timer and
3-44 System/370 Principles of Operation clock-comparator
installed, are
locations 224-231.
224-231 (Real Address)
facility
stored
is
at
Machine-Check Clock-Comparator Save Area: During a machine­
check interruption, the contents
of the clock comparator, if the
CPU-timer and clock-comparator
facility is installed, are stored at locations 224-231.
232-239 (Real Address)
Machine-Cheek-Interruption Code:
During a machine-check interrup­
tion, the machine-cheek-inter­
ruption code is stored at
locations 232-239.
244-247 (Real Address)
External-Damage Code: During a
machine-check interruption due
to certain external-damage
conditions, depending on the
model, an external-damage code
may be stored at locations
244-247.
248-251 (Real Address)
Failing-Storage Address: During
a machine-check interruption, a failing-storage address may be
stored at locations 249-251,
with zeros stored at location
248. When the extended-real­
address facility is installed,
the failing-storage address is 31 bits and bit 0 of location
248 is set to zero.
252-255 (Real Address)
Region Code: During a machine­
check interruption, model­
dependent information may be
stored at locations 252-255.
256-263 (Absolute Address)
Store-Status PSW Save Area:
During the executi~ of~e store-status operation, the
contents of the current PSW are
stored at locations 256-263.
256-351 (Real Address)
Fixed-Logout Area: Depending on
the model, logout information
may be stored at locations
256-351 during a machine-check
interruption or full channel
logout. Additionally, the
contents of locations 256-351
may be changed at any time,
subject to the asynchronous­
fixed-logout-control bit in control register 14.