mation outside the PSW. There may be up
to sixteen 32-bit control registers. One or more specific bit positions in
control registers are assigned to each facility requiring such register space. When the facility is installed, the bits
perform the defined control function.
The LOAD CONTROL instruction causes all
control-register positions within those
registers designated by the instruction
to be loaded from storage. The
instructions LOAD ADDRESS SPACE PARAME­ TERS, SET SECONDARY ASN, PROGRAM CALL, and PROGRAM TRANSFER provide specialized functions to place information into
certain control-register positions.
Information loaded into the control
registers becomes active (that is,
assumes control over the system) at the
completion of the instruction causing
the information to be loaded.
At the time the registers are loaded,
the information is not checked for
exceptions, such as invalid
translation-format code or an address
designating an unavailable or a protected location. The validity of the
information is checked and the exceptions, if any, are indicated at the time the information is used. The STORE CONTROL instruction causes all
control-register positions, within those
registers designated by the instruction,
to be placed in storage. The
instructions EXTRACT PRIMARY ASN, EXTRACT SECONDARY ASN, and PROGRAM CALL provide specialized functions to obtain information from certain control­
register positions. Values corresponding to unassigned or unin­
stalled register positions are unpredictable. Only the general structure of the
control registers is described here; the
definition of a particular control­
register position appears in the
description of the facility with which
the register position is associated.
The figure "Assignment of Control­ Register Fields" shows the control­
register positions which are assigned
and the initial value of the field upon
execution of initial CPU reset. Programming Notes
1. The detailed definition of a particular control-register bit
position can be located by refer­
ring to the entry "control-register assignment" in the Index.
2. To ensure that existing programs
operate correctly if and when new facilities using additional
control-register positions are
installed, the program should load zeros in unassigned control­
register positions. Although STORE CONTROL may provide zeros in the
bit positions corresponding to
unassigned or uninstalled register
positions, the program should not
depend on such zeros. It is
permissible, however, for the program to load into the control
registers any information previous­
ly stored by means of STORE CONTROL. Chapter 4. Control 4-9
Ctrl Initial Reg Bits Name of Field Associated with Value 0 0 Block-multiplexing control Block-multiplexing channels 0 0 1 SSM-suppression control SET SYSTEM MASK 0 0 2 TOD-clock-sync control Multiprocessing 0 0 3 Low-address-protection control Low-address protection 0 0 4 Extraction-authority control Dual-address-space control 0 0 5 Secondary-space control Dual-address-space control 0 0 7 Storage-key-exception control Storage-key 4K-byte block 0 0 8-12 Translation format Dynamic address translation 0 0 14 Vector control
l
Vector operations 0 0 16 Malfunction-alert subclass mask Multiprocessing 0 0 17 Emergency-signal subclass mask Multiprocessing 0 0 18 External-call subclass mask Multiprocessing 0 0 19 TOD-clock sync-check subclass mask Multiprocessing 0 0 20 Clock-comparator subclass mask Clock comparator 0 0 21 CPU-timer subclass masK CPU timer 0 0 22 Service-signal subclass mask Service signal 0 0 24 Interval-timer subclass mask Interval timer 1 0 25 Interrupt-key subclass mask Interrupt key 1 0 26 External-signal subclass mask External signals 1
1 0-7 Primary segment-table length Dynamic address translation 0 1 8-25 Primat·y segment-table origin Dynamic address translation 0 1 31 Space-switch-event control Dual-address-space control 0 2 0-31 Channel masks Channels 1
3 0-15 PSW-key mask Dual-address-space control 0 3 16-31 Secondary ASN Dual-address-space control 0 4 0-15 Authorization index Dual-address-space control 0 4 16-31 Primary i\SN Dual-address-space control 0 5 0 Subsystem-linkage control Dual-address-space control 0 5 8-24 Linkage-table origin Dual-address-space control 0 5 25-31 Linkage-table length Dual-address-space control 0 7 0-7 Secondat·y segment-table length Dual-address-space control 0 7 8-25 Secondory segment-toble origin Dual-address-space control 0 Assignment of Control-Register Fields (Part 1 of 2) 4-10 System/370 Principles of Operation
Previous Page Next Page