channel, and main-storage location can
be in only one configuration at a time.
MAIN STORAGE Main storage, which is directly address­
able, provides for high-speed processing
of data by the CPUs and channels. Both
data and programs must be loaded into
main storage from input devices before
they can be processed. The amount of
main storage available on the system
depends on the model, and, depending on
the model, the amount in the configura­
tion may be under control of model­
dependent configuration controls. The
storage is available in multiples of
2K-byte blocks. When either TEST BLOCK or the storage-key 4K-byte-block facili­
ty is installed, storage is available in multiples of 4K-byte blocks. At any
instant in time, all CPUs and all chan­
nels in the configuration have access to
the same blocks of storage and refer to
a particular block of main-storage
locations by using the same absolute
address.
Main storage may include a faster-access
buffer storage, sometimes called a
cache. Each CPU may have an associated
cache. The effects, except on perform­ ance, of the physical construction and
the use of distinct storage media are
not observable by the prograM.
The central processing unit (CPU) is the
controlling center of the system. It
contains the sequencing and processing
facilities for instruction execution,
interruption action, timing functions, initial program loading, and other
machine-related functions.
The physical implementation of the CPU may differ among models, but the logical
function remains the same. The result
of executing an instruction is the same
for each model, providing that the
program complies with the compatibility
rules.
The CPU, in executing instructions, can
process binary integers and floating­
point numbers of fixed length, decimal
integers of variable length, and logical
information of either fixed or variable
length. Processing may be in parallel
or in series; the width of the process­
ing elements, the multiplicity of the
shifting paths, and the degree of simul­
taneity in performing the different
types of arithmetic differ from one CPU to another without affecting the logical
results.
Instructions which the CPU executes fall
into five classes: general, decimal,
floating-point, control, and I/O instructions. The general instructions
are used in performing binary integer
arithmetic operations and logical,
branching, and other nonarithmetic oper­
ations. The decimal instructions
operate on data in the decimal format,
and the floating-point instructions on
data in the floating-point format. The
privileged control instructions and the I/O instructions can be executed only
when the CPU is in the supervisor state;
the semiprivileged control instructions
can be executed in the problem state,
subject to the appropriate authorization
mechanisms.
To perform its functions, the CPU may
use a certain amount of internal
storage. Although this internal storage
may use the same physical storage medium
as maln storage, it is not considered
part of main storage and is not address­
able by programs.
The CPU provides registers which are
available to programs but do not have
addressable representations in main
storage. They include the current
program-status word (PSW), the general
registers, the floating-point registers,
the control registers, the prefix regis­ ter, and the registers for the clock
comparator and the CPU timer. Each CPU in an installation provides access to a
time-of-day (TOO) clock, which may be
local to that CPU or shared with other CPUs in the installation. The instruc­
tion operation code determines which
type of register is to be used in an
operation. See the figure "General, Floating-Point, and Control Registers" later in this chapter for the format of
those registers. PSW The program-status word (PSW) includes the instruction address, condition code,
and other information used to control
instruction sequencing and to determine
the state of the CPU. The active or
controlling PSW is called the current PSW. It governs the program currently being executed.
The CPU has an interruption capability,
which permits the CPU to switch rapidly
to another program in response to excep­ tional conditions and external stimuli.
When an interruption occurs, the CPU places the current PSW in an assigned storage location, called the old-PSW location, for the particular class of
interruption. The CPU fetches a new PSW from a second assigned storage location.
This new PSW determines the next program
to be executed. When it has finished processing the interruption, the inter- Chapter 2. Organization 2-3

rupting program may reload the old PSW, making it again the current PSW, so that
the interrupted program can continue.
There are six classes of interruption:
external, I/O, machine check, program,
restart, and supervisor call. Each
class has a distinct pair of old-PSW and new-PSW locations permanently assigned
in real storage.
GENERAL REGISTERS Instructions may designate information
in one or more of 16 general registers.
The general registers may be used as
base-address registers and index regis­
ters in address arithmetic and as accu­
mulators in general arithmetic and
logical operations. Each register
contains 32 bits. The general registers
are identified by the numbers 0-15 and
are designated by a four-bit R field in
an instruction. Some instructions
provide for addressing multiple general
registers by having several R fields.
For some instructions, the use of a
specific general register is implied
rather than explicitly designated by an R field of the instruction.
For some operations, two adjacent gener­
al registers are coupled, providing a 64-bit format. In these operations, the
program must designate an even-numbered
register, which contains the leftmost
(high-order) 32 bits. The next higher­ numbered register contains the rightmost
(low-order) 32 bits.
In addition to their use as accumulators in general arithmetic and logical oper­
ations, 15 of the 16 general registers are also used as base-address and index
registers in address generation. In these cases, the registers are desig­
nated by a four-bit B field or X field
in an instruction. A value of zero in
the B or X field specifies that no base or index is to be applied, and, thus,
general register 0 cannot be designated as containing a base address or index. FLOATING-POINT REGISTERS Four floating-point registers are avail­
able for floating-point operations.
They are identified by the numbers 0, 2, 4, and 6 and are designated by a four-
2-4 System/370 Principles of Operation bit R field in floating-point instruc­
tions. Each floating-point register is
64 bits long and can contain either a short (32-bit) or a long (64-bit)
floating-point operand. A short operand
occupies the leftmost bit positions of a floating-point register. The rightmost
portion of the register is ignored in operations that use short operands and
remains unchanged in operations that
produce short results. Two pairs of
adjacent floating-point registers can be
used for extended operands: registers 0 and 2, and registers 4 and 6. Each of
these pairs, identified by the numbers 0 and 4, provides for a 128-bit format. CONTROL REGISTERS The CPU makes provisions for 16 control
registers, each having 32 bit positions.
The bit positions in the registers are
assigned to particular facilities in the
system, such as program-event recording,
and are used either to specify that an
operation can take place or to furnish
special information required by the
facility.
The control registers are identified by
the numbers 0-15 and are designated by
four-bit R fields in the instructions LOAD CONTROL and STORE CONTROL. Multi­ ple control registers can be addressed
by these instructions. VECTOR FACILITY
Depending on the model, a vector facili­
ty may be provided as an extension of the CPU. When the vector facility is
provided on a CPU, it functions as an
integral part of that CPU. The func­
tions of the vector facility and its
registers are described in the publica­
tion IBM System/370 Vector Operations, SA22-7125. Input/output (I/O) operations involve
the transfer of information between main
storage and an I/O device. I/O devices
and their control units attach to chan­
nels, which control this data transfer.