Instruction-Processing Damage
Bit 1 (PO), when one, indicates that
damage has occurred to the instruction
processing of the cpu.
The exact meaning of bit 1 depends on
the setting of the backed-up bit, bit
14. When the backed-up bit is one, the
condition is called processing backup.
When the backed-up bit is zero, the
condition is called processing damage.
These two conditions are described in
the section "Synchronous Machine-Check­
Interruption Conditions" in this
chapter.
Instruction-processing damage can be a
nullifying or a terminating exigent
condition and has no subclass-mask bit.
System Recoverv Bit 2 (SR), when one, indicates that
malfunctions were detected but did not
result in damage or have been success­
fully corrected. Some malfunctions
detected as part of an I/O operation may
result in a system-recovery condition in
addition to an I/O-error condition. The
presence and extent of the system­
recovery capability depend on the model.
System recovery is a repressible condi­ tion. It is masked by the recovery
subclass-mask bit, which is in bit posi­ tion 4 of control register 14. Programming Notes
1. System recovery may be used to
report a failing-storage address
detected by a CPU prefetch or by an I/O operation.
2. Unless the corresponding validity
bits are ones, the indication of
system recovery does not imply
storage logical validity, or that
the fields stored as a result of
the machine-check interruption are
valid.
Interval-Timer Damage
Bit 3 (TO), when one, indicates that
damage has occurred to the interval
timer or to the word at real storage
locations 80-83. Interval-timer damage is a repressible
condition. It 1S masked by the
external-damage subclass-mask bit, which
is in bit position 6 of control register
14.
Timing-Facility Damage
Bit 4 (CD), when one, indicates that
damage has occurred to the TOO clock,
the CPU timer, the clock comparator, or
to the CPU-timer or clock-comparator
external-interruption conditions. The
timing-facility-damage machine-check
condition is set whenever any of the
following occurs:
1. The TOO clock accessed by this CPU enters the error or not-operational
state.
2. The CPU timer is damaged, and the CPU is enabled for CPU-timer external interruptions. On some
models, this condition may be
recognized even when the CPU is not
enabled for CPU-timer interrup­
tions. Depending on the model, the
machine-check condition may be
generated only as the CPU timer enters an error state. Or, the
machine-check condition may be
continuously generated whenever the CPU is enabled for CPU-timer inter­
ruptions, until the CPU timer is
validated.
3. The clock comparator is damaged,
and the CPU is enabled for clock­
comparator external interruptions. On some models, this condition may
be recognized even when the CPU is
not enabled for clock-comparator
interruptions.
Timing-facility damage may also be set
along with instruction-processing damage
when an instruction which accesses the TOO clock, CPU timer, or clock compara­
tor produces incorrect results. Depend­
ing on the model, the CPU timer or clock
comparator may be validated by the
interruption which reports the CPU timer
or clock comparator as invalid.
Timing-facility damage is a repressible
condition. It is masked by the timing­ facility subclass-mask bit, which is in bit position 6 of control register 14. Programming Note
Timing-facility-damage conditions for
the CPU timer and the clock comparator
are not recognized on most models when
these facilities are not in use. The facilities are considered not in use
when the CPU is disabled for the corre­
sponding external interruptions (PSW bit
7, or the subclass-mask bits, bits 20 and 21 of control register 0, are Chapter 11. Machine-Check Handling 11-17

zeros), and when the corresponding set
and store instructions are not executed.
Timing-facility-damage conditions that
are already pending remain pending,
however, when the CPU is disabled for
the corresponding external interruption.
Timing-facility-damage conditions due to
damage to the TOO clock are always
recognized.
External Damage
Bit 5 CEO), when one, indicates that
damage has occurred to a channel or to
storage during operations not directly
associated with processing the current
instruction. Channel malfunctions are
reported as external damage only when the channel is unable to report the
malfunctions by an I/O-error condition.
Depending on the model and on the type
and extent of the error, an external­
damage condition may be indicated as
system damage instead of external
damage.
When bit 5, external damage, is one and
bit 26, external-damage-code validity,
is also one, the external-damage code
has been stored to indicate, in more detail, the cause of the external-damage
machine-check interruption. When the
external damage cannot be isolated to
one or more of the conditions as defined
in the external-damage code, or when the
detailed indication for the condition is
not implemented by the model, external
damage is indicated with bit 26 set to
zero. The presence and extent of
reporting external damage depend on the
model.
External damage is a repressible condi­
tion. It is masked by the external­
damage subclass-mask bit, which is in
bit position 6 of control register 14.
Vector-Facility Failure
Bit 6 (VF) of the machine-check­
interruption code, when one, indicates
that the vector facility has failed to
such an extent that the service process­
or has made the facility not available.
This bit may be set to one regardless of
whether the vector-control bit, bit 14
of control register A, is one or zero.
Vector-facility failure is a repressible
condition and has no subclass-mask bit.
11-18 System/370 Principles of Operation Degradation
Bit 7 COG), when one, indicates that
continuous degradation of system
performance, more serious than that
indicated by system recovery, has
occurred. Degradation may be reported
when system-recovery conditions exceed a
machine-preestablished threshold or when unit deletion has occurred. The pres­
ence and extent of the degradation­
report capability depend on the model.
Degradation is a repressible condition.
It is masked by the degradation
subclass-mask bit, which is in bit posi­
tion 5 of control register 14.
Warning
Bit 8 (W), when one, i ndi cates' that
damage is imminent in some part of the
system (for example, that power is about
to fail, or that a loss of cooling is
occurring). Whether warning conditions
are recognized depends on the model.
If the condition responsible for the
imminent damage is removed before the interruption request is honored (for
example, if power is restored), the
request does not remain pending, and no
interruption occurs. Conversely, the
request is not cleared by the inter­
ruption, and, if the condition persists,
more than one interruption may result
from the same condition.
Warning is a repressible condition •. It is masked by the warning subclass-mask
bit, which is in bit position 7 of
control register 14.
Service-Processor Damage
Bit 10 (SP), when one, indicates that
damage has occurred to the service
processor. Service-processor damage may
be made pending at all CPUs in the
configuration, or it may be detected
independently by each CPU. The presence
and extent of reporting service­
processor damage depend on the model.
Service-processor damage is a repressi­
ble condition and has no subclass-mask
bit. SUBCLASS MODIFIERS
Bits 13 (VS), 14 (B), 15 (D), and 34
(DA) of the machine-check-interruption
code act as modifiers to the subclass
bits.