The cause of the interruption is identi­ fied by the interruption code. When the
old PSW specifies the EC mode, the
interruption code is placed at real
locations 142-143, the instruction­
length code is placed in bit positions 5
and 6 of the byte at real location 141
with the rest of the bits set to zeros, and zeros are stored at real location 140. When the old PSW specifies the BC mode, the interruption code and the ILC are placed in the old PSW. For some
causes, additional information identify­
ing the reason for the interruption is stored at real locations 144-159 in both
the EC and BC modes.
Except for PER events, the condition
causing the interruption is indicated by
a coded value placed in the rightmost
seven bit positions of the interruption
code. Only one condition at a time can
be indicated. Bits 0-7 of the inter­
ruption code are set to zeros.
PER events are indicated by setting bit
8 of the interruption code to one. When
this is the only condition, bits 0-7 and
9-15 are also set to zeros. When a PER
event is indicated concurrently with
another program-interruption condition,
bit 8 is one, and the coded value for
the other condition is indicated in bit
positions 0-7 and 9-15. When there is a corresponding mask bit,
a program interruption can occur only
when that mask bit is one. The program
mask in the PSW controls four of the
exceptions, bit 1 in control register 0 controls whether SET SYSTEM MASK causes
a special-operation exception, bits
16-31 in control register 8 control
interruptions due to monitor events,
and, in the EC mode, a hierarchy of
masks control interruptions due to PER
events. When any controlling mask bit is zero, the condition is ignored; the
condition does not remain pending.
Programming Notes 1. When the new PSW for a program
interruption has a PSW-format error
or causes an exception to be recog­ nized in the process of instruction
fetching, a string of program
interruptions may occur. See the
section "Priority of Interruptions"
in this chapter for a description
of how such strings are terminated.
2. Some of the conditions indicated as
program exceptions may be recog­
nized also by a channel, in which
case the exception is indicated in
the channel-status word. EXCEPTION-EXTENSION CODE When an arithmetic exception is recog­
nized during execution of an interrupti­
ble vector instruction, a nonzero
exception-extension code is stored in bits 0-7 of the program-interruption
code. This code is set to a nonzero
value only for arithmetic exceptions
occurring during the execution of vector
instructions. For more details, see the
publication IBM System/370 Vector Oper­ ations, SA22-7125. PROGRAM-INTERRUPTION CONDITIONS The following is a detailed description
of each program-interruption condition.
Addressing Exception
An addressing exception is recognized
when the CPU attempts to reference a
main-storage location that is not avail­
able in the configuration. A main­
storage location is not available in the
configuration when the location is not
installed, when the storage unit is not
in the configuration, or when power is
off in the storage unit. An address
designating a storage location that is
not available in the configuration is
referred to as invalid. The operation is suppressed when the
address of the instruction is invalid.
Similarly, the operation is suppressed
when the address of the target instruc­
tion of EXECUTE is invalid. Also, the
unit of operation is suppressed when an
addressing exception is encountered in
accessing a table entry. The table
entries to which the rule applies are entries for the segment table, page
table, linkage table, entry table, ASN
first table, ASN second table, authority
table, trace-table designation, trace­
table-entry header, and CPU-identity byte. Addressing exceptions result in
suppression when they are encountered
for references to the segment table and
page table, in both implicit references
for dynamic address translation and
references associated with the execution
of LOAD REAL ADDRESS and TEST PROTECTION. Except for some specific
instructions whose execution is suppressed, the operation is terminated
for an operand address that can be
translated but designates an unavailable
location. See the figure "Summary of
Action for Addressing and Protection
Exceptions."
For termination, changes may occur only
to result fields. In this context, the
term "result field" includes the condi- Chapter 6. Interruptions 6-15

tion code, registers, and any storage
locations that are provided and that are
designated to be changed by the instruc­
tion. Therefore, if an instruction is
due to change only the contents of a
field in storage, and every byte of the
field is in a location that is not
available in the configuration, the
operation is suppressed. When part of
an operand location is available in the
configuration and part is not, storing
may be performed in the part that is
available in the configuration. When an addressing exception occurs
during the fetching of an instruction or
during the fetching of a OAT table entry
associated with an instruction fetch, it
is unpredictable whether the IlC is 1,
6-16 System/370 Principles of Operation 2, or 3. When the exception is associ­ ated with fetching the target of EXECUTE, the IlC is 2.
In all cases of addressing exceptions
not associated with instruction
fetching, the IlC is 1, 2, or 3, indi­
cating the length of the instruction
that caused the reference. However, on
some models without the translation
facility, an IlC of 0 occurs when an
addressing exception is recognized for a
store-type reference. An addressing exception is indicated by
a program-interruption code of 0005 hex (or 0085 hex if a concurrent PER event
is indicated).