3. Shift amounts from 31 to 63 cause
the entire numeric part to be
shifted out of the register, leav­
ing a result of the maximum nega­
tive number or zero, depending on
whether or not the initial contents
were negative.
SHIFT LEFT SINGLE LOGICAL SLL [RS] '89'
o 8 12 16 20 31
The 32-bit first operand is shifted left
the number of bits specified by the
second-operand address, and the result is placed at the first-operand location.
Bits 12-15
ignored.
of the instruction are
The second-operand address is not used
to address data; its rightmost six bits
indicate the number of bit positions to
be shifted. The remainder of the
address is ignored.
All 32 bits of the first operand partic­
ipate in the shift. Bits shifted out of
bit position 0 are not inspected and are
lost. Zeros are supplied to the vacated
bit positions on the right. Condition Code: The code remains
unchanged.
Program Exceptions: None.
SHIFT RIGHT DOUBLE SRDA [RS] '8E'
o 8 12 16 20 31
The 63-bit numeric part of the signed
first operand is shifted right the
number of bits specified by the second­
operand address, and the result is
placed at the first-operand location.
Bits 12-15
ignored.
of the instruction are
The R\ field designates an even-odd pair
of general registers and must designate
an even-numbered register; otherwise, a
specification exception is recognized.
The second-operand address is not used
to address data; its rightmost six bits
indicate the number of bit positions to
be shifted. The remainder of the
address is ignored.
The first operand is treated as a 64-bit
signed binary integer. The sign posi­
tion of the even-numbered register
remains unchanged. The leftmost bit
position of the odd-numbered register
contains a numeric bit, which partic­
ipates in the shift in the same manner
as the other numeric bits. Bits shifted
out of bit position 31 of the odd­
numbered register are not inspected and
are lost. Bits equal to the sign are
supplied to the vacated bit positions on
the left.
Resulting Condition Code: o
1
2
3
Result zero
Result less than zero
Result greater than zero
Program Exceptions: Specification SHIFT RIGHT DOUBLE LOGICAL SRDL [RS) '8C' o 8 12 16 20 31
The 64-bit first operand is shifted
right the number of bits specified by
the second-operand address, and the
result is placed at the first-operand
location. Bits 12-15
ignored.
of the instruction are
The R\ field designates an even-odd pair of general registers and must designate
an even-numbered register; otherwise, a
specification exception is recognized.
The second-operand address is not used
to address data; its rightmost six bits
indicate the number of bit positions to
be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand partic­
ipate in the shift. Bits shifted out of
bit position 31 of the odd-numbered
register are not inspected and are lost. Zeros are supplied to the vacated bit
positions on the left. Condition Code: unchanged.
Program Exceptions:
Specification
The code remains Chapter 7. General Instructions 7-33

SHIFT RIGHT SINGLE SRA [RS] '8A'
o 8 12 16 20 31
The 31-bit numeric part of the signed
first operand is shifted right the
number of bits specified by the second­
operand address, and the result is
placed at the first-operand location.
Bits 12-15
ignored.
of the instruction are
The second-operand address is not used
to address data; its rightmost six bits
indicate the number of bit positions to
be shifted. The remainder of the
address is ignored.
The first operand is treated as a 32-bit
signed binary integer. The sign of the
first operand remains unchanged. All 31
numeric bits of the operand participate
in the right shift. Bits shifted out of
bit position 31 are not inspected and
are lost. Bits equal to the sign are
supplied to the vacated bit positions on
the left.
Resulting Condition Code:
o
1
2
3
Result zero
Result less than zero
Result greater than zero
Program Exceptions: None.
ProQramming Notes
1. A right shift of one bit position
is equivalent to division by 2 with
rounding downward. When an even
number is shifted right one posi­
tion, the result is equivalent to
dividing the number by 2. When an
odd number is shifted right one
position, the result is equivalent
to dividing the next lower number
by 2. For example, +5 shifted
right by one bit position yields
+2, whereas -5 yields -3.
2. Shift amounts from 31 to 63 cause
the entire numeric part to be
shifted out of the register, leav­
ing a result of -1 or zero, depend­
ing on whether or not the initial
contents were negative.
7-34 System/370 Principles of Operation SHIFT RIGHT SINGLE LOGICAL SRL [RS] '88'
o 8 12 16 20 31
The 32-bit first operand is shifted
right the number of bits specified by
the second-operand address, and the
result is placed at the first-operand
location.
Bits 12-15
ignored.
of the instruction are
The second-operand address is not used
to address data; its rightmost six bits indicate the number of bit positions to
be shifted. The remainder of the
address is ignored.
All 32 bits of the first operand partic­
ipate in the shift. Bits shifted out of
bit position 31 are not inspected and
are lost. Zeros are supplied to the
vacated bit positions on the left.
Condition Code:
unchanged.
The code
Program Exceptions: None. STORE ST [RX] '50' o 8 12 16 20 remains
31
The first operand is stored at the
second-operand location.
The 32 bits in the general register are
placed unchanged at the second-operand
location.
Condition Code:
unchanged.
Program Exceptions:
The code
Access (store, operand 2) STORE CHARACTER
[RX]
'42' I R, I X2 I B2
o 8 12 16 20 remains
31