device or the indication of the reasons
for which anI/O operation has been
concluded. TheCSW is formed, or parts
ofit are replaced, in the process of I/O interruptions and possibly during
the execution ofSTART I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, HALT DEVICE, and STORE CHANNEL ID.
TheCSW is stored at real storage
location 64 and is available to the
program at this location until the time
the nextI/O interruption occurs or
until anotherI/O instruction causes its
contents to be replaced, whichever
occurs first.
The information placed in theCSW by an I/O interruption pertains to the channel
and device which are identified by theI/O address stored during the inter
ruption. The information placed in theCSW by START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, HALT DEVICE, or STORE CHANNEL ID
pertains to the channel and (except forSTORE CHANNEL ID) the device addressed
by the instruction.
TheCSW has the following format: IKeylslllccl CCW Address 0 4 6 8 31 Count 32 40 48 63
The fields in theCSW are allocated as
follows:
Subchannel Key: Bits0-3 form the
access key used in the chain of oper
ations at the subchannel.Suspended Bit 4, when stored as
one, indicates that the subchannel asso
ciated with the information in theCSW has the execution of a channel program
currently suspended. TheS condition
can only be indicated in theCSW stored
as a result of anI/O interruption
because of the program-controlled
interruption(PCI) condition.
logout Pending(1): Bit 5, when one,
indicates that anI/O instruction cannot
be executed until a logout has been
cleared. Bit 45, channel-control check,
will always be one when bit 5 is one.
DeferredCondition Code eCC): Bits 6
and 7 indicate whether situations have
been encountered subsequent to the
setting of a condition code0 for START I/O FAST RELEASE or RESUME I/O that
would have caused a different
condition-code setting forSTART I/O. The possible setting of these bits, and
their meanings, are as follows:Setting of
Bit 6 Bit 7 Meaning0 0 Normal I/O interruption 0 1 Deferred condition code
i s 1
10 (Reserved)
1 1 Deferred condition code
is 3CCW Address: Bits 8-31 form an absolute
address that is 8 higher than the
address of the lastCCW used. Status: Bits 32-47 identify the status
of the device and the channel that
caused the storing of theCSW. Bits
32-39, the unit status, indicate situ
ations detected by the device or control
unit. Bits40-47, the channel status,
are provided by the channel and indicate
situations associated with the subchan
nel. The 16 bits are designated as
follows:
Bit Designation
32 Attention
33Status modifier
34 Control-unit end
35 Busy
36Channel end
37 Device end
38Unit check
39Unit exception 40 Program-controlled interruption
41 Incorrect length
42 Program check
43 Protection check
44 Channel-data check
45 Channel-control check
46 Interface-control check
47Chaining check Count: Bits 48-63 form the
count for the lastCCW used. UNIT STATUS residual
The following status indications are
generated by theI/O device or control
unit. The timing and causes of these
status indications for each type of
device are specified in theSl publica
tion for the device.
When theI/O device is accessible from
more than one channel, status due to
channel-initiated operations is signaled
to the channel that initiated the asso
ciatedI/O operation. The handling of
status not associated withI/O oper- Chapter 13. Input/Output Operations 13-63
for which an
concluded. The
of
the execution of
The
location 64 and is available to the
program at this location until the time
the next
until another
contents to be replaced, whichever
occurs first.
The information placed in the
and device which are identified by the
ruption. The information placed in the
pertains to the channel and (except for
by the instruction.
The
The fields in the
follows:
Subchannel Key: Bits
access key used in the chain of oper
ations at the subchannel.
one, indicates that the subchannel asso
ciated with the information in the
currently suspended. The
can only be indicated in the
as a result of an
because of the program-controlled
interruption
logout Pending
indicates that an
be executed until a logout has been
cleared. Bit 45, channel-control check,
will always be one when bit 5 is one.
Deferred
and 7 indicate whether situations have
been encountered subsequent to the
setting of a condition code
would have caused a different
condition-code setting for
their meanings, are as follows:
Bit 6 Bit 7 Meaning
i s 1
1
1 1 Deferred condition code
is 3
address that is 8 higher than the
address of the last
of the device and the channel that
caused the storing of the
32-39, the unit status, indicate situ
ations detected by the device or control
unit. Bits
are provided by the channel and indicate
situations associated with the subchan
nel. The 16 bits are designated as
follows:
Bit Designation
32 Attention
33
34 Control-unit end
35 Busy
36
37 Device end
38
39
41 Incorrect length
42 Program check
43 Protection check
44 Channel-data check
45 Channel-control check
46 Interface-control check
47
count for the last
The following status indications are
generated by the
unit. The timing and causes of these
status indications for each type of
device are specified in the
tion for the device.
When the
more than one channel, status due to
channel-initiated operations is signaled
to the channel that initiated the asso
ciated
status not associated with